Abstract: A transceiver configured to communicate a burst of data bits and meta-data bits for the data bits includes data channels, auxiliary data channels, and at least one error correction channel. The transceiver includes an encoder that applies 11b7s encoding to a first number of the data bits to generate first PAM-3 symbols on some or all of the communication channels, and that applies 3b2s encoding to a second number of the data bits to generate second PAM-3 symbols on at least some of the communication channels.

Abstract: Data bits are encoded in one or both of an eleven bit seven pulse amplitude modulated three-level (PAM-3) symbol (11b7s) format and a three bit two symbol (3b2s) format on a plurality of data channels and on an error correction channel. One or more of a cyclic redundancy check (CRC) value, a poison value, and a severity value are encoded as 11b7s and/or 3b2s PAM-3 symbols on the error correction channel.

Abstract: Data bits are encoded in one or both of an eleven bit seven pulse amplitude modulated three-level (PAM-3) symbol (11b7s) format and a three bit two symbol (3b2s) format on a plurality of data channels, one or more auxiliary data channels, and an error correction channel. One or more of a cyclic redundancy check (CRC) value, a poison value, and a severity value are encoded as 11b7s and/or 3b2s PAM-3 symbols on an error correction channel.

Abstract: A transceiver configured to communicate a burst of data bits and meta-data bits for the data bits includes data channels, auxiliary data channels, and at least one error correction channel. The transceiver includes an encoder that applies 11b7s encoding to a first number of the data bits to generate first PAM-3 symbols on some or all of the communication channels, and that applies 3b2s encoding to a second number of the data bits to generate second PAM-3 symbols on at least some of the communication channels.

Abstract: Data bits are encoded in an eleven bit seven pulse amplitude modulated three-level (PAM-3) symbol format on a plurality of data channels and two auxiliary data channels, and one or more of a cyclic redundancy check (CRC) value, a poison value, and a severity value are encoded as PAM-3 symbols on an error correction channel.

Abstract: Data bits are encoded in an eleven bit seven pulse amplitude modulated three-level (PAM-3) symbol format on a plurality of data channels and two auxiliary data channels, and one or more of a cyclic redundancy check (CRC) value, a poison value, and a severity value are encoded as PAM-3 symbols on an error correction channel.

Abstract: This disclosure provides a multi-layered printed circuit board (PC) that has signal array region. The signal array region has a width and circumscribes a power core region and has signal vias connected to respective signal ball pads, and ground vias connected to respective ground ball pads within the signal array region that have an associated ball pad pitch. The PCB also has an inner current power layer. The signal and ground vias are arranged on the component layer in a pattern and extend into the inner current layer. The pattern forms current power paths across the width of the signal array region, such that the current power paths have a width that is at least about 50% as wide as the ball pad pitch.

Abstract: First symbols are generated on a plurality of data channels by applying PAM-N encoding on a first subset of bits of a data burst, the first symbols generated without maximum transitions; second symbols are generated on at least one optionally-activated additional data channel, the second symbols generated by applying the PAM-N encoding on a second subset of bits of the data burst, the second symbols generated without maximum transitions; and third symbols are generated on a channel for communicating error correction bits for the first bits and second bits, the third symbols generated by applying hybrid PAM-N encoding on the error correction bits and a third subset of bits of the data burst, the hybrid PAM-N encoding comprising an interleaving of symbols with N voltage levels and symbols with less than N voltage levels.

Abstract: This disclosure provides a multi-layered printed circuit board (PC) that has signal array region. The signal array region has a width and circumscribes a power core region and has signal vias connected to respective signal ball pads, and ground vias connected to respective ground ball pads within the signal array region that have an associated ball pad pitch. The PCB also has an inner current power layer. The signal and ground vias are arranged on the component layer in a pattern and extend into the inner current layer. The pattern forms current power paths across the width of the signal array region, such that the current power paths have a width that is at least about 50% as wide as the ball pad pitch.

Abstract: Techniques for limiting the growth of errors in decoded data words that arise from bit errors incurred during transmission. The growth of 3+ bit errors in the decoded data word is limited at the expense of a higher number of two bit errors, which are correctable using practical error correcting codes.

Abstract: Provided is a method used by an electronic device to determine a cause of a trend in vital sign data, the method including: obtaining vital sign data of a target; determining a trend over time in the vital sign data; and determining a cause having a highest possibility of causing the determined trend, based on one or more possible causes of the determined trend and one or more stored weights for the possible cause, wherein the one or more stored weights each represent a possibility that the one or more possible causes of the determined trend is a cause responsible for the determined trend.

Abstract: Embodiments of the present invention reconstruct a waveform at a receiver-end of a channel from an observed waveform physically measured at a probe point near the middle of the channel, where the channel is corrupted by reflections. The channel may be a memory channel of a high-speed I/O interface, for example. Equations to derive the waveform may be created using linear network analysis and/or signal processing, for example. S-parameters may be derived from simulated models representing components from the probe point to the load. The s-parameters together with the load impedance are used to recreate the desired waveform free from corruption due to reflections.

Abstract: Systems and methods that facilitate resistance and capacitance balancing are presented. In one embodiment, a system comprises: a plurality of ground lines configured to ground components; and a plurality of signal bus lines interleaved with the plurality of ground lines, wherein the interleaving is configured so that plurality of signal bus lines and plurality of ground lines are substantially evenly spaced and the plurality of signal bus lines convey a respective plurality of signals have similar resistance and capacitance constants that are balanced. The plurality of signals can see a substantially equal amount ground surface and have similar amounts of capacitance. The plurality of signal bus lines can have similar cross sections and lengths with similar resistances. The plurality of signal bus lines interleaved with the plurality of ground lines can be included in a two copper layer interposer design with one redistribution layer (RDL).

Abstract: An encoding process for bus data utilizes data from multiple data line groups on a multi-byte wide bus where each group has an associated DBI line. The process leverages the expanded encoding space for the multiple groups and associated multiple DBI bits. This process may be expanded to four bytes, eight bytes, etc.

Abstract: In one embodiment, a system comprises: a plurality of aggressor bus lines; and a plurality of differential pair bus lines that are located in relatively parallel close proximity to the plurality of aggressor bus lines, wherein at least two of the plurality of differential pair bus lines change location with respect to each other at a point that has a cancelling affect on cross talk from the plurality of aggressor bus lines, wherein the change includes cross over routing. The plurality of differential pair bus lines can convey differential clock signals. The routing of the plurality of differential pair bus lines is substantially parallel to one another before and after the change.

Abstract: A circuit includes a splitter to extract L bits from each of a plurality of N-bit transmissions on a data bus, a decoder to generate output data comprising N-L bits of each N-bit transmission, and a delay circuit to apply the L bits for a previous transmission to control the inversion of a current transmission at the decoder.

Abstract: An encoding process for bus data utilizes data from multiple data line groups on a multi-byte wide bus where each group has an associated DBI line. The process leverages the expanded encoding space for the multiple groups and associated multiple DBI bits. This process may be expanded to four bytes, eight bytes, etc.

Abstract: A PAM-4 communication process divides a full burst of raw data into two half bursts, extracts a bit from each half burst and communicating the extracted bit on a DBI line, and encodes the remaining bits of the half burst to avoid maximum transitions between PAM-4 symbols on a data line.

Abstract: A PAM-4 communication process divides a full burst of raw data into two half bursts, extracts a bit from each half burst and communicating the extracted bit on a DBI line, and encodes the remaining bits of the half burst to avoid maximum transitions between PAM-4 symbols on a data line.

Abstract: In one embodiment, a system comprises: a plurality of aggressor bus lines; and a plurality of differential pair bus lines that are located in relatively parallel close proximity to the plurality of aggressor bus lines, wherein at least two of the plurality of differential pair bus lines change location with respect to each other at a point that has a cancelling affect on cross talk from the plurality of aggressor bus lines, wherein the change includes cross over routing. The plurality of differential pair bus lines can convey differential clock signals. The routing of the plurality of differential pair bus lines is substantially parallel to one another before and after the change.