Abstract: In one embodiment, a system comprises: a plurality of aggressor bus lines; and a plurality of differential pair bus lines that are located in relatively parallel close proximity to the plurality of aggressor bus lines, wherein at least two of the plurality of differential pair bus lines change location with respect to each other at a point that has a cancelling affect on cross talk from the plurality of aggressor bus lines, wherein the change includes cross over routing. The plurality of differential pair bus lines can convey differential clock signals. The routing of the plurality of differential pair bus lines is substantially parallel to one another before and after the change.

Abstract: Systems and methods that facilitate resistance and capacitance balancing are presented. In one embodiment, a system comprises: a plurality of ground lines configured to ground components; and a plurality of signal bus lines interleaved with the plurality of ground lines, wherein the interleaving is configured so that plurality of signal bus lines and plurality of ground lines are substantially evenly spaced and the plurality of signal bus lines convey a respective plurality of signals have similar resistance and capacitance constants that are balanced. The plurality of signals can see a substantially equal amount ground surface and have similar amounts of capacitance. The plurality of signal bus lines can have similar cross sections and lengths with similar resistances. The plurality of signal bus lines interleaved with the plurality of ground lines can be included in a two copper layer interposer design with one redistribution layer (RDL).

Abstract: A PAM-4 communication process divides a full burst of raw data into two half bursts, extracts a bit from each half burst and communicating the extracted bit on a DBI line, and encodes the remaining bits of the half burst to avoid maximum transitions between PAM-4 symbols on a data line.

Abstract: Embodiments of the present invention reconstruct a waveform at a receiver-end of a channel from an observed waveform physically measured at a probe point near the middle of the channel, where the channel is corrupted by reflections. The channel may be a memory channel of a high-speed I/O interface, for example. Equations to derive the waveform may be created using linear network analysis and/or signal processing, for example. S-parameters may be derived from simulated models representing components from the probe point to the load. The s-parameters together with the load impedance are used to recreate the desired waveform free from corruption due to reflections.

Abstract: A memory driver, a method of driving a command bus for a synchronous dual data rate (sDDR) memory and a memory controller for controlling dynamic random-access memory (DRAM). In one embodiment, the memory driver includes: (1) pull-up and pull-down transistors couplable to a command bus of a memory controller and operable in 1N and 2N timing modes and (2) gear down offset circuitry coupled to the pull-up transistor and operable to offset the command bus when transitioning out of the 1N timing mode and increase an extent and duration of 1-0-1 transitions on the command bus.

Abstract: A method of providing a user with a battery power notification in a mobile device and the mobile device therefor are provided. The method includes determining a future application to be run on the mobile device, determining whether a remaining battery life of the mobile device is enough to run the future application, based on a power consumption of a preceding application running before the future application, and outputting a notification indicating a battery insufficiency of the mobile device in response to the determining that the remaining battery life is not enough.

Abstract: A method of providing a user with a battery power notification in a mobile device and the mobile device therefor are provided. The method includes determining a future application to be run on the mobile device, determining whether a remaining battery life of the mobile device is enough to run the future application, based on a power consumption of a preceding application running before the future application, and outputting a notification indicating a battery insufficiency of the mobile device in response to the determining that the remaining battery life is not enough.

Abstract: A memory driver, a method of driving a command bus for a synchronous dual data rate (sDDR) memory and a memory controller for controlling dynamic random-access memory (DRAM). In one embodiment, the memory driver includes: (1) pull-up and pull-down transistors couplable to a command bus of a memory controller and operable in 1N and 2N timing modes and (2) gear down offset circuitry coupled to the pull-up transistor and operable to offset the command bus when transitioning out of the 1N timing mode and increase an extent and duration of 1-0-1 transitions on the command bus.

Abstract: Systems and methods for encoding a data word using an 8b/9b encoding scheme that eliminates two-aggressor crosstalk are disclosed. The 8b/9b encoding scheme enables a data word that can be subdivided into portions of eight bits or less to be encoded using code words having one extra bit than the corresponding portion of the data word. Each of the valid code words does not include any three consecutive bits having a logic level of logic-high (i.e., ‘1’), and represent transition vectors for consecutive symbols transmitted over the high speed parallel bus. An encoder and corresponding decoder are disclosed for implementing the 8b/9b encoding scheme. In one embodiment, the encoder/decoder implements a modified Fibonacci sequence algorithm. In another embodiment, the encoder/decoder implements a look-up table. In some embodiments, data words may be less than eight bits wide.

Abstract: Systems and methods for encoding/decoding a data word using an 8b/9b encoding scheme that eliminates two-aggressor crosstalk are disclosed. The 8b/9b encoding scheme enables a data word to be encoded using code words. Each of the valid code words does not include any three consecutive bits having a logic level of logic-high (i.e., ‘1’), and represent transition vectors for consecutive symbols transmitted over the high speed parallel bus. An encoder and corresponding decoder are disclosed for implementing the 8b/9b encoding scheme. In one embodiment, the encoder/decoder implements a modified Fibonacci sequence algorithm. In another embodiment, the encoder/decoder implements a look-up table.

Abstract: Systems and methods for encoding a data word using an 8b/9b encoding scheme that eliminates two-aggressor crosstalk are disclosed. The 8b/9b encoding scheme enables a data word that can be subdivided into portions of eight bits or less to be encoded using code words having one extra bit than the corresponding portion of the data word. Each of the valid code words does not include any three consecutive bits having a logic level of logic-high (i.e., ‘1’), and represent transition vectors for consecutive symbols transmitted over the high speed parallel bus. An encoder and corresponding decoder are disclosed for implementing the 8b/9b encoding scheme. In one embodiment, the encoder/decoder implements a modified Fibonacci sequence algorithm. In another embodiment, the encoder/decoder implements a look-up table. In some embodiments, data words may be less than eight bits wide.

Abstract: Systems and methods for encoding/decoding a data word using an 8b/9b encoding scheme that eliminates two-aggressor crosstalk are disclosed. The 8b/9b encoding scheme enables a data word to be encoded using code words. Each of the valid code words does not include any three consecutive bits having a logic level of logic-high (i.e., ‘1’), and represent transition vectors for consecutive symbols transmitted over the high speed parallel bus. An encoder and corresponding decoder are disclosed for implementing the 8b/9b encoding scheme. In one embodiment, the encoder/decoder implements a modified Fibonacci sequence algorithm. In another embodiment, the encoder/decoder implements a look-up table.