Abstract: A semiconductor includes a gate structure on a substrate and including a gate electrode, a source/drain pattern on a side surface of the gate electrode, a source/drain contact connected to the source/drain pattern, a first etching stop film structure on the source/drain contact and the gate structure, the first etching stop film structure including a first lower etching stop film and a silicon nitride film on the first lower etching stop film, and a first via plug inside the first etching stop film structure and connected to the source/drain contact, wherein the first lower etching stop film includes aluminum, and wherein an upper surface of the silicon nitride film is on a same plane as an upper surface of the first via plug.

Abstract: A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer.

Abstract: A semiconductor device includes: a first active pattern extended in a first direction on a substrate; a second active pattern extended in the first direction and spaced apart from the first active pattern in a second direction on the substrate; a field insulating layer between the first active pattern and the second active pattern on the substrate; a first gate electrode on the first active pattern; a second gate electrode on the second active pattern; and a gate isolation structure separating the first gate electrode and the second gate electrode from each other on the field insulating layer, wherein a width of the gate isolation structure in the second direction varies in a downward direction from the upper isolation pattern.

Abstract: A semiconductor device may include first and second fin-shaped patterns on a substrate, that extend in a first direction, and are spaced apart from each other in a second direction. A first epitaxial pattern may be on the first fin-shaped pattern, and a second epitaxial pattern may be on the second fin-shaped pattern. A field insulating layer may be on the substrate, and may cover a sidewall of the first fin-shaped pattern, a sidewall of the second fin-shaped pattern, a part of a sidewall of the first epitaxial pattern, and a part of a sidewall of the second epitaxial pattern. The top surface of the field insulating layer may be higher than the bottom surface of the first epitaxial pattern and the bottom surface of the second epitaxial pattern.

Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a first fin-type pattern and a second fin-type pattern on a substrate, a first epitaxial pattern on the first fin-type pattern, a second epitaxial pattern on the second fin-type pattern, and a lower field insulating film on the substrate and extends on a sidewall of the first fin-type pattern and a sidewall of the second fin-type pattern, wherein the lower field insulating film includes a protrusion protruding in a third direction. The protrusion of the lower field insulating film may be between the first fin-type pattern and the second fin-type pattern, and a vertical level of a top surface of the protrusion of the lower field insulating film increases and then decreases with increasing distance from the sidewall of the first fin-type pattern.

Abstract: A semiconductor device includes a substrate, a gate structure, a source/drain pattern, first and second interlayer insulating layers, a first via plug connected to the source/drain pattern, and an etch stop structure layer, which may include a plurality of etch stop layers sequentially stacked. The etch stop structure layer may have a structure in relation to other components that improves aspects of the semiconductor device.

Abstract: A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer.

Abstract: A semiconductor device comprising: a lower insulating layer; a field insulating layer on the lower insulating layer; an upper insulating layer on the field insulating layer; a first through via in the upper insulating layer; a second through via in the field insulating layer; and a third through via in the lower insulating layer, wherein the second through via is connected to the first and third through vias, and wherein a width of a top surface of the second through via is greater than a width of a bottom surface of the first through via, a width of a bottom surface of the second through via is greater than a width of a top surface of the third through via, and a width of a middle portion of the second through via is greater than the widths of the top surface and the bottom surface of the second through via.

Abstract: A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer.

Abstract: A semiconductor device includes a first active pattern extending in a first direction on a substrate, and a second active pattern extending in the first direction on the substrate, the second active pattern spaced apart from the first active pattern in a second direction. The device includes a field insulating film between the first active pattern and the second active pattern on the substrate, a first gate electrode intersecting the first active pattern on the substrate, a second gate electrode intersecting the second active pattern on the substrate, and a gate separation structure on the field insulating film. The gate separation structure separates the first gate electrode and the second gate electrode from each other, the gate separation structure includes a plurality of first sub-insulating films and at least one second sub-insulating film, and the at least one second sub-insulating film is between the first sub-insulating films.

Abstract: A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer.

Abstract: A semiconductor device includes: a first active pattern extended in a first direction on a substrate; a second active pattern extended in the first direction and spaced apart from the first active pattern in a second direction on the substrate; a field insulating layer between the first active pattern and the second active pattern on the substrate; a first gate electrode on the first active pattern; a second gate electrode on the second active pattern; and a gate isolation structure separating the first gate electrode and the second gate electrode from each other on the field insulating layer, wherein a width of the gate isolation structure in the second direction varies in a downward direction from the upper isolation pattern.

Abstract: A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer.

Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a first fin-type pattern and a second fin-type pattern on a substrate, a first epitaxial pattern on the first fin-type pattern, a second epitaxial pattern on the second fin-type pattern, and a lower field insulating film on the substrate and extends on a sidewall of the first fin-type pattern and a sidewall of the second fin-type pattern, wherein the lower field insulating film includes a protrusion protruding in a third direction. The protrusion of the lower field insulating film may be between the first fin-type pattern and the second fin-type pattern, and a vertical level of a top surface of the protrusion of the lower field insulating film increases and then decreases with increasing distance from the sidewall of the first fin-type pattern.

Abstract: A semiconductor includes a gate structure on a substrate and including a gate electrode, a source/drain pattern on a side surface of the gate electrode, a source/drain contact connected to the source/drain pattern, a first etching stop film structure on the source/drain contact and the gate structure, the first etching stop film structure including a first lower etching stop film and a silicon nitride film on the first lower etching stop film, and a first via plug inside the first etching stop film structure and connected to the source/drain contact, wherein the first lower etching stop film includes aluminum, and wherein an upper surface of the silicon nitride film is on a same plane as an upper surface of the first via plug.

Abstract: A semiconductor device comprises a gate structure including a gate electrode, on a substrate, a source/drain pattern disposed on a side surface of the gate electrode, on the substrate, a first interlayer insulating layer on the gate structure, a first via plug disposed in the first interlayer insulating layer and connected to the source/drain pattern, an etch stop structure layer including first to third etch stop layers sequentially stacked, on the first interlayer insulating layer, such that the second etch stop layer is between the first etch stop layer and the third etch stop layer, a second interlayer insulating layer contacting the etch stop structure layer, on the etch stop structure layer, such that the etch stop structure layer is between the first interlayer insulating layer and the second interlayer insulating layer, and a wire line disposed in the second interlayer insulating layer and contacting the first via plug.

Abstract: A semiconductor device may include first and second fin-shaped patterns on a substrate, that extend in a first direction, and are spaced apart from each other in a second direction. A first epitaxial pattern may be on the first fin-shaped pattern, and a second epitaxial pattern may be on the second fin-shaped pattern. A field insulating layer may be on the substrate, and may cover a sidewall of the first fin-shaped pattern, a sidewall of the second fin-shaped pattern, a part of a sidewall of the first epitaxial pattern, and a part of a sidewall of the second epitaxial pattern. The top surface of the field insulating layer may be higher than the bottom surface of the first epitaxial pattern and the bottom surface of the second epitaxial pattern.

Abstract: A method of manufacturing a semiconductor device includes forming first and second pattern structures on first and second regions of a substrate, respectively; forming a preparatory first interlayer insulating layer covering the first pattern structure on the first region; forming a preparatory second interlayer insulating layer covering the second pattern structure on the second region, the preparatory second interlayer insulating layer including first colloid; and converting the preparatory first and second interlayer insulating layers into first and second interlayer insulating layers, respectively, by annealing the preparatory first and second interlayer insulating layers.

Abstract: A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer.

Abstract: A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer.