Patents by Inventor Supreet Jeloka
Supreet Jeloka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11966785Abstract: A method for controlling hardware resource configuration for a processing system comprises obtaining performance monitoring data indicative of processing performance associated with workloads to be executed on the processing system, providing a trained machine learning model with input data depending on the performance monitoring data; and based on an inference made from the input data by the trained machine learning model, setting control information for configuring the processing system to control an amount of hardware resource allocated for use by at least one processor core. A corresponding method of training the model is provided. This is particularly useful for controlling inter-core borrowing of resource between processor cores in a multi-core processing system, where resource is borrowed between respective cores, e.g. cores on different layers of a 3D integrated circuit.Type: GrantFiled: July 30, 2020Date of Patent: April 23, 2024Assignee: Arm LimitedInventors: Dam Sunwoo, Supreet Jeloka, Saurabh Pijuskumar Sinha, Jaekyu Lee, Jose Alberto Joao, Krishnendra Nathella
-
Publication number: 20240036923Abstract: Aspects of the present disclosure relate to an apparatus comprising a plurality of processing elements having a spatial layout, and control circuitry to assign workloads to said plurality of processing elements. The control circuitry is configured to, based on a timing parameter, determine one or more active processing elements to deactivate; determine, based on the spatial layout, one or more inactive processing elements to activate; and deactivate said one or more active processing elements and activate said one or more inactive processing elements.Type: ApplicationFiled: July 27, 2022Publication date: February 1, 2024Inventors: Rishav ROY, Supreet JELOKA, Shidhartha DAS, Rahul MATHUR
-
Publication number: 20230317126Abstract: According to one implementation of the present disclosure, a circuit comprises: a memory array comprising one or more groupings of bitcells, one or more bitlines, and one or more wordlines; and one or more canary circuits coupled to the memory array, wherein each of the canary circuits is configured to predict at least partial breakdown of a corresponding grouping of bitcells in the memory array. According to one implementation of the present disclosure, a method includes: providing an excitation stress on one or more canary circuits corresponding to a grouping of bitcells in a memory array; detecting at least a partial breakdown of the one or more canary circuits; and generating a flag.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Inventors: Fernando GarcĂa Redondo, Pranay Prabhat, Mudit Bhargava, Supreet Jeloka
-
Patent number: 11693796Abstract: Various implementations described herein are directed to a device having a multi-layered logic structure with a first logic layer and a second logic layer arranged vertically in a stacked configuration. The device may have a memory array that provides data, and also, the device may have an inter-layer data bus that vertically couples the memory array to the multi-layered logic structure. The inter-layer data bus may provide multiple data paths to the first logic layer and the second logic layer for reuse of the data provided by the memory array.Type: GrantFiled: May 31, 2021Date of Patent: July 4, 2023Assignee: Arm LimitedInventors: Paul Nicholas Whatmough, Zhi-Gang Liu, Supreet Jeloka, Saurabh Pijuskumar Sinha, Matthew Mattina
-
Patent number: 11682432Abstract: Various implementations described herein are related to a device having voltage regulation architecture with multiple layers arranged in a multi-layer structure. The device may include one or more layers of the multiple layers with voltage regulation circuitry that may be configured to manage at least one of process variation and temperature variation between the multiple layers of the multi-layer structure.Type: GrantFiled: June 10, 2021Date of Patent: June 20, 2023Assignee: Arm LimitedInventors: Supreet Jeloka, Saurabh Pijuskumar Sinha, Shidhartha Das, Mudit Bhargava, Rahul Mathur
-
Patent number: 11569824Abstract: Various implementations described herein are directed to a device with a voltage-controlled oscillator that receives an enable signal, receives a reset signal, and provides internal pulse signals including one or more coarse internal pulse signals and multiple fine internal pulse signals. The device may have a coarse sampler that receives the one or more coarse internal pulse signal and provides a coarse sampled output signal. The device may have a fine sampler that receives the multiple fine internal pulse signals and provides a fine sampled output signal.Type: GrantFiled: June 10, 2021Date of Patent: January 31, 2023Assignee: Arm LimitedInventors: Shidhartha Das, Yunpeng Cai, Supreet Jeloka
-
Publication number: 20220399895Abstract: Various implementations described herein are directed to a device with a voltage-controlled oscillator that receives an enable signal, receives a reset signal, and provides internal pulse signals including one or more coarse internal pulse signals and multiple fine internal pulse signals. The device may have a coarse sampler that receives the one or more coarse internal pulse signal and provides a coarse sampled output signal. The device may have a fine sampler that receives the multiple fine internal pulse signals and provides a fine sampled output signal.Type: ApplicationFiled: June 10, 2021Publication date: December 15, 2022Inventors: Shidhartha Das, Yunpeng Cai, Supreet Jeloka
-
Patent number: 11526305Abstract: A memory for an artificial neural network (ANN) accelerator is provided. The memory includes a first bank, a second bank and a bank selector. Each bank includes at least two word lines and a plurality of read word selectors. Each word line stores a plurality of words, and each word has a plurality of bytes. Each read word selector has a plurality of input ports and an output port, is coupled to a corresponding word in each word line, and is configured to select a byte of the corresponding word of a selected word line based on a byte select signal. The bank selector is coupled to the read word selectors of the first bank and the second bank, and configured to select a combination of read word selectors from at least one of the first bank and the second bank based on a bank select signal.Type: GrantFiled: November 24, 2020Date of Patent: December 13, 2022Assignee: Arm LimitedInventors: Mudit Bhargava, Paul Nicholas Whatmough, Supreet Jeloka, Zhi-Gang Liu
-
Publication number: 20220391469Abstract: According to one implementation of the present disclosure, a method includes performing a spatial alignment of at least one of first or second data tiers of a circuit; and performing a computation based on the spatial alignment of the at least one of the first and second data tiers. According to another implementation of the present disclosure, a circuit includes: a compute circuitry; and at least first and second data tiers of two or more data tiers positioned at least partially overlapping one another. In an example, each of the at least first and second data tiers is coupled to the compute circuitry. In certain implementations, the positioning of the first and second data tiers at least partially overlapping one another corresponds to a spatial alignment.Type: ApplicationFiled: June 4, 2021Publication date: December 8, 2022Inventors: Supreet Jeloka, Mudit Bhargava, Saurabh Pijuskumar Sinha, Rahul Mathur
-
Patent number: 11521680Abstract: An integrated circuit includes a primary memory array with cells switchable between first and second states. The circuit also includes sacrificial memory cells; each fabricated to be switchable between the first and second states and associated with at least one row of the primary array. A controller is configured to detect a write operation to a row of the primary array, stress a sacrificial cell associated with the row and detect a failure of the associated sacrificial cell. The sacrificial cells are fabricated to have lower write-cycle endurance than cells of the primary array or are subjected to more stress. Failure of a row of the primary array is predicted based, at least in part, on a detected failure of the associated sacrificial cell.Type: GrantFiled: December 31, 2020Date of Patent: December 6, 2022Assignee: Arm LimitedInventors: Fernando Garcia Redondo, Mudit Bhargava, Pranay Prabhat, Supreet Jeloka
-
Publication number: 20220382690Abstract: Various implementations described herein are directed to a device having a multi-layered logic structure with a first logic layer and a second logic layer arranged vertically in a stacked configuration. The device may have a memory array that provides data, and also, the device may have an inter-layer data bus that vertically couples the memory array to the multi-layered logic structure. The inter-layer data bus may provide multiple data paths to the first logic layer and the second logic layer for reuse of the data provided by the memory array.Type: ApplicationFiled: May 31, 2021Publication date: December 1, 2022Inventors: Paul Nicholas Whatmough, Zhi-Gang Liu, Supreet Jeloka, Saurabh Pijuskumar Sinha, Matthew Mattina
-
Publication number: 20220351032Abstract: A compute-in-memory (CIM) array module and a method for performing dynamic saturation detection for a CIM array are provided. The CIM array module includes a CIM array, saturation detection units (SDUs) and a controller. The CIM array includes selectable row signal lines, column signal lines and cells. Each cell is located at an intersection of a selectable row signal line and a column signal line, and each cell has a programmable conductance. The SDUs are selectively coupled to at least one column signal line, and each SDU is configured to, for each column signal line, generate an analog signal, and identify the column signal line as a saturated column signal line when a voltage of the analog signal is greater than a saturation threshold voltage, or a current of the analog signal is greater than a saturation threshold current.Type: ApplicationFiled: April 28, 2021Publication date: November 3, 2022Applicant: Arm LimitedInventors: Teyuh Alice Chou, Mudit Bhargava, Supreet Jeloka, Fernando Garcia Redondo, Paul Nicholas Whatmough
-
Publication number: 20220343045Abstract: Various implementations described herein refer to a device having an integrated circuit with multiple tiers including a first tier and a second tier that are arranged vertically in a stacked configuration. The first tier may have first functional components, and the second tier may have second functional components. The device may have a three-dimensional (3D) connection within the first tier that allows for synchronous signaling between the first functional components and the second functional components for reducing latency between the multiple tiers including the first tier and the second tier.Type: ApplicationFiled: October 8, 2021Publication date: October 27, 2022Inventors: Rainer Herberholz, Supreet Jeloka
-
Patent number: 11409617Abstract: Various implementations described herein are related to a device having energy harvesting circuitry that experiences power failures. The device may include computing circuitry having a processor coupled to the energy harvesting circuitry. The processor may be configured to reduce a number of write operations to a log structure having a hardware bit-vector used by the computing circuitry to boost computational progress even with the power failures.Type: GrantFiled: May 22, 2020Date of Patent: August 9, 2022Assignee: Arm LimitedInventors: Emily Kathryn Ruppel, Supreet Jeloka, Parameshwarappa Anand Kumar Savanth, Wei Wang
-
Publication number: 20220208265Abstract: An integrated circuit includes a primary memory array with cells switchable between first and second states. The circuit also includes sacrificial memory cells; each fabricated to be switchable between the first and second states and associated with at least one row of the primary array. A controller is configured to detect a write operation to a row of the primary array, stress a sacrificial cell associated with the row and detect a failure of the associated sacrificial cell. The sacrificial cells are fabricated to have lower write-cycle endurance than cells of the primary array or are subjected to more stress. Failure of a row of the primary array is predicted based, at least in part, on a detected failure of the associated sacrificial cell.Type: ApplicationFiled: December 31, 2020Publication date: June 30, 2022Applicant: Arm LimitedInventors: Fernando Garcia Redondo, Mudit Bhargava, Pranay Prabhat, Supreet Jeloka
-
Publication number: 20220199125Abstract: Various implementations described herein are related to a device having voltage regulation architecture with multiple layers arranged in a multi-layer structure. The device may include one or more layers of the multiple layers with voltage regulation circuitry that may be configured to manage at least one of process variation and temperature variation between the multiple layers of the multi-layer structure.Type: ApplicationFiled: June 10, 2021Publication date: June 23, 2022Inventors: Supreet Jeloka, Saurabh Pijuskumar Sinha, Shidhartha Das, Mudit Bhargava, Rahul Mathur
-
Publication number: 20220172762Abstract: Various implementations described herein are related to a method. The method may apply a write control voltage to a bitcell. The method may gradually ramp the write control voltage to the bitcell. The method may terminate application of the write control voltage to the bitcell when a write operation is sensed in the bitcell.Type: ApplicationFiled: November 30, 2020Publication date: June 2, 2022Inventors: Supreet Jeloka, Mudit Bhargava, Pranay Prabhat, Femando Garcia Redondo
-
Publication number: 20220164127Abstract: A memory for an artificial neural network (ANN) accelerator is provided. The memory includes a first bank, a second bank and a bank selector. Each bank includes at least two word lines and a plurality of write word selectors. Each word line stores a plurality of words, and each word has a plurality of bytes. Each write word selector has an input port and a plurality of output ports, is coupled to a corresponding word in each word line, and is configured to select a byte of the corresponding word of a selected word line based on a byte select signal. The bank selector is coupled to the write word selectors of the first bank and the second bank, and configured to select a combination of write word selectors from at least one of the first bank and the second bank based on a bank select signal.Type: ApplicationFiled: November 24, 2020Publication date: May 26, 2022Applicant: Arm LimitedInventors: Mudit Bhargava, Paul Nicholas Whatmough, Supreet Jeloka, Zhi-Gang Liu
-
Publication number: 20220164137Abstract: A memory for an artificial neural network (ANN) accelerator is provided. The memory includes a first bank, a second bank and a bank selector. Each bank includes at least two word lines and a plurality of read word selectors. Each word line stores a plurality of words, and each word has a plurality of bytes. Each read word selector has a plurality of input ports and an output port, is coupled to a corresponding word in each word line, and is configured to select a byte of the corresponding word of a selected word line based on a byte select signal. The bank selector is coupled to the read word selectors of the first bank and the second bank, and configured to select a combination of read word selectors from at least one of the first bank and the second bank based on a bank select signal.Type: ApplicationFiled: November 24, 2020Publication date: May 26, 2022Applicant: Arm LimitedInventors: Mudit Bhargava, Paul Nicholas Whatmough, Supreet Jeloka, Zhi-Gang Liu
-
Publication number: 20220035679Abstract: A method for controlling hardware resource configuration for a processing system comprises obtaining performance monitoring data indicative of processing performance associated with workloads to be executed on the processing system, providing a trained machine learning model with input data depending on the performance monitoring data; and based on an inference made from the input data by the trained machine learning model, setting control information for configuring the processing system to control an amount of hardware resource allocated for use by at least one processor core. A corresponding method of training the model is provided. This is particularly useful for controlling inter-core borrowing of resource between processor cores in a multi-core processing system, where resource is borrowed between respective cores, e.g. cores on different layers of a 3D integrated circuit.Type: ApplicationFiled: July 30, 2020Publication date: February 3, 2022Inventors: Dam SUNWOO, Supreet JELOKA, Saurabh Pijuskumar SINHA, Jaekyu LEE, Jose Alberto JOAO, Krishnendra NATHELLA