Abstract: A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.

Abstract: A early bus grant prediction technique combines the operating advantages of both a split transaction bus and a simple shared bus. When a read request is generated by a memory access requester, an early bus request is generated for the impending data transfer. The early bus request is provided to bus grant prediction and arbitration logic that determines whether or not the bus will be available at the time the requested data has been retrieved and is ready for transfer. If the bus is available, the retrieved data is routed immediately to the memory bus for a fly-by transfer. On the other hand, if the bus is not available, the data is routed to a FIFO buffer to be transferred when the bus is available.