Patents by Inventor Suresh Nagarajan
Suresh Nagarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230395166Abstract: Techniques for preventing read disturb in NAND memory devices are described. In one example, reads are tracked for sub-groups. When the number of reads to a sub-group meets a threshold, the data at the wordline on which the threshold was met is moved along with the data at neighboring wordlines to an SLC block without moving the entire block. The performance impact and write amplification impact of read disturb mitigation can be significantly reduced while maintaining some data continuity.Type: ApplicationFiled: August 18, 2023Publication date: December 7, 2023Applicant: Intel CorporationInventors: Arun Sitaram ATHREYA, Shankar NATARAJAN, Sriram NATARAJAN, Yihua ZHANG, Suresh NAGARAJAN
-
Patent number: 11783893Abstract: Programming a multilevel cell (MLC) nonvolatile (NV) media can be performed with internal buffer reuse to reduce the need for external buffering. The internal buffer is on the same die as the NV media to be programmed, along with a volatile memory to store data to program. The internal buffer is to read and program data for the NV media. Programming of the NV media includes staging first partial pages in the buffer for program, reading second partial pages from the NV media to the volatile memory, storing second partial pages in the buffer, and programming the NV media with the first partial pages and the second partial pages.Type: GrantFiled: December 23, 2020Date of Patent: October 10, 2023Assignee: Intel CorporationInventors: Shankar Natarajan, Suresh Nagarajan, Aliasgar S. Madraswala, Yihua Zhang
-
Patent number: 11769557Abstract: Techniques for preventing read disturb in NAND memory devices are described. In one example, reads are tracked for sub-groups. When the number of reads to a sub-group meets a threshold, the data at the wordline on which the threshold was met is moved along with the data at neighboring wordlines to an SLC block without moving the entire block. The performance impact and write amplification impact of read disturb mitigation can be significantly reduced while maintaining some data continuity.Type: GrantFiled: December 16, 2019Date of Patent: September 26, 2023Assignee: Intel CorporationInventors: Arun Sitaram Athreya, Shankar Natarajan, Sriram Natarajan, Yihua Zhang, Suresh Nagarajan
-
Patent number: 11582174Abstract: Techniques for determining when to store content and when to refrain from storing content are described herein. In some instances, devices exchange communications that include different types of content, such as text, audio data, video data, image data, or the like. For instance, a first device may receive, from a second device, a communication that includes audio data representing speech of a user of the second device, along with text for display on the first device. The text may comprise a transcription of the audio file, additional commentary provided by the user of the second device, or the like. Upon receiving the communication that includes text and audio data, the first device may determine whether or not to store the audio data. For instance, the first device may determine whether it currently stores this audio content. If so, then the first device may refrain from storing the content again.Type: GrantFiled: February 24, 2017Date of Patent: February 14, 2023Assignee: Amazon Technologies, Inc.Inventors: Suresh Nagarajan Srinivasan, Lakshminarayanan Vijayaraghavan
-
Method and apparatus to improve write bandwidth of a block-based multi-level cell nonvolatile memory
Patent number: 11237732Abstract: Write performance of a block-based multi-level cell non-volatile memory is increased through the use of an internal copy of blocks with a high validity. Write (program) performance for sequential workloads is increased by moving the data in blocks with a high validity within a NAND device directly from the portion of the NAND device configured as single level cell NAND to the portion of the NAND device configured as multi-level cell NAND.Type: GrantFiled: August 6, 2019Date of Patent: February 1, 2022Assignee: Intel CorporationInventors: Shankar Natarajan, Suresh Nagarajan, Yihua Zhang -
Publication number: 20220004495Abstract: Systems, apparatuses, and methods provide for a memory controller to manage cache evictions and/or insertions in a data server environment based at least in part on host managed hotness data. For example, a memory controller includes logic to receive a plurality of read and write requests from a host, where the plurality of read and write requests include an associated hotness data. A valid unit count of operational memory cells is maintained on a block-by-block basis for a plurality of memory blocks. A hotness index count is also maintained based at least in part on the hotness data on a block-by-block basis for the plurality of memory blocks. One or more memory blocks of the plurality of memory blocks are selected for eviction from a single level cell region to an x-level cell region based at least in part on the valid unit count and the hotness index count.Type: ApplicationFiled: September 15, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventors: Shankar Natarajan, Chace Clark, Francis Corrado, Shivashekar Muralishankar, Suresh Nagarajan
-
Patent number: 11119672Abstract: An embodiment of a memory controller device includes technology to control access to a memory array which includes a single-level cell region and a multi-level cell region, determine an amount of valid data in a dynamic portion of the single-level cell region at runtime, and adjust a size of the dynamic portion of the single-level cell region at runtime based on the determined amount of valid data in the dynamic portion of the single-level cell region. Other embodiments are disclosed and claimed.Type: GrantFiled: August 6, 2019Date of Patent: September 14, 2021Assignee: Intel CorporationInventors: Shankar Natarajan, Suresh Nagarajan, Shivashekar Muralishankar, Sriram Natarajan, Yihua Zhang
-
Publication number: 20210151098Abstract: Programming a multilevel cell (MLC) nonvolatile (NV) media can be performed with internal buffer reuse to reduce the need for external buffering. The internal buffer is on the same die as the NV media to be programmed, along with a volatile memory to store data to program. The internal buffer is to read and program data for the NV media. Programming of the NV media includes staging first partial pages in the buffer for program, reading second partial pages from the NV media to the volatile memory, storing second partial pages in the buffer, and programming the NV media with the first partial pages and the second partial pages.Type: ApplicationFiled: December 23, 2020Publication date: May 20, 2021Inventors: Shankar NATARAJAN, Suresh NAGARAJAN, Aliasgar S. MADRASWALA, Yihua ZHANG
-
Patent number: 10996860Abstract: An apparatus for controlling a solid state drive (SSD) includes an host interface, to receive a set of memory access commands from a host computer, and processing circuitry coupled to the host interface and to memory cells of the SSD, to distinguish the write commands from the read commands in the set, and execute up to a threshold number of the write commands prior to executing any of the read commands.Type: GrantFiled: October 31, 2018Date of Patent: May 4, 2021Assignee: Intel CorporationInventors: Suresh Nagarajan, Shankar Natarajan
-
Publication number: 20210109587Abstract: Power management circuitry in the solid state drive monitors activity on the plurality of media channels to coordinate an active period and an idle period using credits to manage a power budget for the solid state drive. The power management circuitry to coordinate active and idle periods across components in a workload pipeline in the solid state drive for a given performance target to obtain an optimal power and thermal profile.Type: ApplicationFiled: December 21, 2020Publication date: April 15, 2021Inventors: Anoop MUKKER, Romesh TRIVEDI, Suresh NAGARAJAN
-
Publication number: 20210097004Abstract: A solid state drive with a Logical To Physical (L2P) indirection table stored in a persistent memory is provided. The L2P indirection table has a plurality of entries, each entry to store a physical block address in the block addressable memory assigned to a logical block address. The solid state drive including solid state drive controller circuitry communicatively coupled to the persistent memory and the block addressable memory. The solid state drive controller circuitry including a volatile memory to store a logical to physical address indirection table cache and circuitry to monitor the logical to physical address indirection table cache and to write dirty logical to physical entries in the logical to physical address indirection table cache to the logical to physical address indirection table in the persistent memory.Type: ApplicationFiled: December 15, 2020Publication date: April 1, 2021Inventors: Suresh NAGARAJAN, Scott CRIPPIN, Sahar KHALILI, Shankar NATARAJAN, Romesh TRIVEDI
-
Publication number: 20210096778Abstract: Dirty Logical-to-Physical (L2P) entries in an L2P indirection table stored in a host volatile memory buffer are flushed to non-volatile memory in the solid state drive through the use of a write-back mode based on flush checkpoints. The use of write-back mode to flush dirty entries in the L2P indirection table to non-volatile memory in the solid state drive based on flush checkpoints results in an increase in the write bandwidth of the solid state drive.Type: ApplicationFiled: December 15, 2020Publication date: April 1, 2021Inventors: Suresh NAGARAJAN, Anoop MUKKER, Shankar NATARAJAN, Romesh TRIVEDI
-
Patent number: 10877686Abstract: An apparatus is described that includes a solid state drive having non volatile buffer memory and non volatile primary storage memory. The non volatile buffer memory is to store less bits per cell than the non volatile primary storage memory. The solid state drive includes a controller to flush the buffer in response to a buffer flush command received from a host. The controller is to cause the solid state drive to service read/write requests that are newly received from the host in between flushes of smaller portions of the buffer's content that are performed to service the buffer flush command.Type: GrantFiled: April 13, 2018Date of Patent: December 29, 2020Assignee: Intel CorporationInventors: Shankar Natarajan, Romesh Trivedi, Suresh Nagarajan, Sriram Natarajan
-
Publication number: 20200167089Abstract: An embodiment of a memory controller device includes technology to control access to a memory array which includes a single-level cell region and a multi-level cell region, determine an amount of valid data in a dynamic portion of the single-level cell region at runtime, and adjust a size of the dynamic portion of the single-level cell region at runtime based on the determined amount of valid data in the dynamic portion of the single-level cell region. Other embodiments are disclosed and claimed.Type: ApplicationFiled: August 6, 2019Publication date: May 28, 2020Applicant: Intel CorporationInventors: Shankar Natarajan, Suresh Nagarajan, Shivashekar Muralishankar, Sriram Natarajan, Yihua Zhang
-
Patent number: 10650886Abstract: Systems, apparatuses and methods may provide for technology to determine a programmable eviction ratio associated with a storage device and convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio. In one example, the amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.Type: GrantFiled: February 28, 2019Date of Patent: May 12, 2020Assignee: Intel CorporationInventors: Shankar Natarajan, Sriram Natarajan, Suresh Nagarajan, Ramkarthik Ganesan, Arun S. Athreya, Romesh B. Trivedi
-
Publication number: 20200118636Abstract: Techniques for preventing read disturb in NAND memory devices are described. In one example, reads are tracked for sub-groups. When the number of reads to a sub-group meets a threshold, the data at the wordline on which the threshold was met is moved along with the data at neighboring wordlines to an SLC block without moving the entire block. The performance impact and write amplification impact of read disturb mitigation can be significantly reduced while maintaining some data continuity.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Arun Sitaram ATHREYA, Shankar NATARAJAN, Sriram NATARAJAN, Yihua ZHANG, Suresh NAGARAJAN
-
Publication number: 20190361614Abstract: Write performance of a block-based multi-level cell non-volatile memory is increased through the use of an internal copy of blocks with a high validity. Write (program) performance for sequential workloads is increased by moving the data in blocks with a high validity within a NAND device directly from the portion of the NAND device configured as single level cell NAND to the portion of the NAND device configured as multi-level cell NAND.Type: ApplicationFiled: August 6, 2019Publication date: November 28, 2019Inventors: Shankar NATARAJAN, Suresh NAGARAJAN, Yihua ZHANG
-
Publication number: 20190267080Abstract: Systems, apparatuses and methods may provide for technology to determine a programmable eviction ratio associated with a storage device and convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio. In one example, the amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.Type: ApplicationFiled: February 28, 2019Publication date: August 29, 2019Inventors: Shankar Natarajan, Sriram Natarajan, Suresh Nagarajan, Ramkarthik Ganesan, Arun S. Athreya, Romesh B. Trivedi
-
Patent number: 10379782Abstract: Systems, apparatuses and methods may provide for technology that writes a block of data addressed within a host managed cache region into a set of multi-level non-volatile memory (NVM) cells organized into a dynamic single level cell buffer region, that writes a block of data addressed outside the host managed cache region into the set of multi-level NVM cells organized into a static single level cell buffer region, and automatically writes the contents of the static single level cell buffer region into the dynamic multi-level NVM media region. The host manage cache region comprises a set of dynamic single level NVM cells within the dynamic multi-level NVM media region, and the multi-level NVM cells are to be dynamically convertible into and from single NVM cells.Type: GrantFiled: August 18, 2017Date of Patent: August 13, 2019Assignee: Intel CorporationInventors: Suresh Nagarajan, Sriram Natarajan, Shankar Natarajan, Jason B. Akers
-
Patent number: 10229735Abstract: Systems, apparatuses and methods may provide for technology to determine a programmable eviction ratio associated with a storage device and convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio. In one example, the amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.Type: GrantFiled: December 22, 2017Date of Patent: March 12, 2019Assignee: Intel CorporationInventors: Shankar Natarajan, Sriram Natarajan, Suresh Nagarajan, Ramkarthik Ganesan, Arun S. Athreya, Romesh B. Trivedi