Patents by Inventor Suresh Nagarajan

Suresh Nagarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190065075
    Abstract: An apparatus for controlling a solid state drive (SSD) includes an host interface, to receive a set of memory access commands from a host computer, and processing circuitry coupled to the host interface and to memory cells of the SSD, to distinguish the write commands from the read commands in the set, and execute up to a threshold number of the write commands prior to executing any of the read commands.
    Type: Application
    Filed: October 31, 2018
    Publication date: February 28, 2019
    Inventors: Suresh Nagarajan, Shankar Natarajan
  • Publication number: 20190056886
    Abstract: Systems, apparatuses and methods may provide for technology that writes a block of data addressed within a host managed cache region into a set of multi-level non-volatile memory (NVM) cells organized into a dynamic single level cell buffer region, that writes a block of data addressed outside the host managed cache region into the set of multi-level NVM cells organized into a static single level cell buffer region, and automatically writes the contents of the static single level cell buffer region into the dynamic multi-level NVM media region. The host manage cache region comprises a set of dynamic single level NVM cells within the dynamic multi-level NVM media region, and the multi-level NVM cells are to be dynamically convertible into and from single NVM cells.
    Type: Application
    Filed: August 18, 2017
    Publication date: February 21, 2019
    Applicant: Intel Corporation
    Inventors: Suresh Nagarajan, Sriram Natarajan, Shankar Natarajan, Jason B. Akers
  • Publication number: 20190042140
    Abstract: An apparatus is described that includes a solid state drive having non volatile buffer memory and non volatile primary storage memory. The non volatile buffer memory is to store less bits per cell than the non volatile primary storage memory. The solid state drive includes a controller to flush the buffer in response to a buffer flush command received from a host. The controller is to cause the solid state drive to service read/write requests that are newly received from the host in between flushes of smaller portions of the buffer's content that are performed to service the buffer flush command.
    Type: Application
    Filed: April 13, 2018
    Publication date: February 7, 2019
    Inventors: Shankar NATARAJAN, Romesh TRIVEDI, Suresh NAGARAJAN, Sriram NATARAJAN
  • Patent number: 7603531
    Abstract: According to some embodiments, use of a shutdown object during system initialization is disclosed. The shutdown object may be read from a non-volatile memory device and loaded into a random access memory. A plurality of headers may then be scanned from the non-volatile memory device. The shutdown object may be referenced to determine whether each of the plurality of headers includes valid data. Each of the plurality of headers that includes valid data may be represented in the random access memory.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: October 13, 2009
    Assignee: Intel Corporation
    Inventors: Vinod K. Puvvada, Neil A. Gabriel, Suresh Nagarajan
  • Publication number: 20080235435
    Abstract: According to some embodiments, use of a shutdown object during system initialization is disclosed. The shutdown object may be read from a non-volatile memory device and loaded into a random access memory. A plurality of headers may then be scanned from the non-volatile memory device. The shutdown object may be referenced to determine whether each of the plurality of headers includes valid data. Each of the plurality of headers that includes valid data may be represented in the random access memory.
    Type: Application
    Filed: March 22, 2007
    Publication date: September 25, 2008
    Inventors: Vinod K. Puvvada, Neil A. Gabriel, Suresh Nagarajan
  • Patent number: 7246195
    Abstract: Logical units of allocation may be designated as overhead and unallocated and made unavailable for use. During one or more write operations, when one or more logical unit is invalidated, one or more of the unallocated overhead logical units may be designated as available for use and one or more of the invalidated logical units may be designated as overhead.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: July 17, 2007
    Assignee: Intel Corporation
    Inventors: Dale Craig Barfuss, Suresh Nagarajan
  • Publication number: 20070100852
    Abstract: A file management system for utilizing both NOR and NAND flash memory technology in a system is disclosed. Control structures are stored within NOR flash memory blocks. Data structures are stored within NAND flash memory blocks.
    Type: Application
    Filed: November 3, 2005
    Publication date: May 3, 2007
    Inventors: Jeffrey Wang, Suresh Nagarajan, John Rudelic
  • Publication number: 20060294292
    Abstract: Various embodiments of the invention may share a single spare block among multiple volumes in a memory that has block erase characteristics, such as a flash memory.
    Type: Application
    Filed: June 27, 2005
    Publication date: December 28, 2006
    Inventors: Ajith Illendula, Suresh Nagarajan
  • Publication number: 20060149893
    Abstract: Logical units of allocation may be designated as overhead and unallocated and made unavailable for use. During one or more write operations, when one or more logical unit is invalidated, one or more of the unallocated overhead logical units may be designated as available for use and one or more of the invalidated logical units may be designated as overhead.
    Type: Application
    Filed: December 30, 2004
    Publication date: July 6, 2006
    Inventors: Dale Barfuss, Suresh Nagarajan