Patents by Inventor Suresh Ramarajan

Suresh Ramarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210375670
    Abstract: An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.
    Type: Application
    Filed: August 12, 2021
    Publication date: December 2, 2021
    Inventors: Xiaosong Zhang, Yongjun J. Hu, David A. Kewley, Md Zahid Hossain, Michael J. Irwin, Daniel Billingsley, Suresh Ramarajan, Robert J. Hanson, Biow Hiem Ong, Keen Wah Chow
  • Patent number: 11101171
    Abstract: An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Xiaosong Zhang, Yongjun J. Hu, David A. Kewley, Md Zahid Hossain, Michael J. Irwin, Daniel Billingsley, Suresh Ramarajan, Robert J. Hanson, Biow Hiem Ong, Keen Wah Chow
  • Patent number: 11088017
    Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John B. Matovu, David S. Meyaard, Gowrisankar Damarla, Sri Sai Sivakumar Vegunta, Kunal Shrotri, Shashank Saraf, Kevin R. Gast, Jivaan Kishore Jhothiraman, Suresh Ramarajan, Lifang Xu, Rithu K. Bhonsle, Rutuparna Narulkar, Matthew J. King
  • Publication number: 20210050252
    Abstract: An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.
    Type: Application
    Filed: August 16, 2019
    Publication date: February 18, 2021
    Inventors: Xiaosong Zhang, Yongjun J. Hu, David A. Kewley, Md Zahid Hossain, Michael J. Irwin, Daniel Billingsley, Suresh Ramarajan, Robert J. Hanson, Biow Hiem Ong, Keen Wah Chow
  • Patent number: 10720569
    Abstract: A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material, a conductive second magnetic electrode spaced from the first electrode and comprising magnetic reference material, and a non-magnetic tunnel insulator material between the first and second electrodes. The magnetic reference material of the second electrode comprises a synthetic antiferromagnetic construction comprising two spaced magnetic regions one of which is closer to the tunnel insulator material than is the other. The one magnetic region comprises a polarizer region comprising CoxFeyBz where “x” is from 0 to 90, “y” is from 10 to 90, and “z” is from 10 to 50. The CoxFeyBz is directly against the tunnel insulator. A non-magnetic region comprising an Os-containing material is between the two spaced magnetic regions. The other magnetic region comprises a magnetic Co-containing material. Other embodiments are disclosed.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: July 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Wei Chen, Witold Kula, Manzar Siddik, Suresh Ramarajan, Johnathan D. Harms
  • Publication number: 20200203220
    Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material.
    Type: Application
    Filed: March 2, 2020
    Publication date: June 25, 2020
    Inventors: John B. Matovu, David S. Meyaard, Gowrisankar Damarla, Sri Sai Sivakumar Vegunta, Kunal Shrotri, Shashank Saraf, Kevin R. Gast, Jivaan Kishore Jhothiraman, Suresh Ramarajan, Lifang Xu, Rithu K. Bhonsle, Rutuparna Narulkar, Matthew J. King
  • Patent number: 10600682
    Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: John B. Matovu, David S. Meyaard, Gowrisankar Damarla, Sri Sai Sivakumar Vegunta, Kunal Shrotri, Shashank Saraf, Kevin R. Gast, Jivaan Kishore Jhothiraman, Suresh Ramarajan, Lifang Xu, Rithu K. Bhonsle, Rutuparna Narulkar, Matthew J. King
  • Patent number: 10439131
    Abstract: A semiconductor device comprises an array of magnetic cell structures each comprising a magnetic tunnel junction over an electrode on a substrate. Each of the magnetic tunnel junctions includes a magnetic material over the substrate, a first tunnel barrier material over the magnetic material, a second tunnel barrier material over the annealed first tunnel barrier material, and another magnetic material over the second tunnel barrier material. Each magnetic tunnel junction is configured to exhibit a tunnel magnetoresistance greater than or equal to about 180% at a resistance area product of less than about 8 ohm ?m2. The semiconductor device also includes another electrode over the another magnetic material. Semiconductor devices including the magnetic tunnel junctions, methods of forming the magnetic tunnel junctions, and methods of forming semiconductor devices including the magnetic tunnel junctions are disclosed.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Manzar Siddik, Witold Kula, Suresh Ramarajan
  • Publication number: 20190305211
    Abstract: A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material, a conductive second magnetic electrode spaced from the first electrode and comprising magnetic reference material, and a non-magnetic tunnel insulator material between the first and second electrodes. The magnetic reference material of the second electrode comprises a synthetic antiferromagnetic construction comprising two spaced magnetic regions one of which is closer to the tunnel insulator material than is the other. The one magnetic region comprises a polarizer region comprising CoxFeyBz where “x” is from 0 to 90, “y” is from 10 to 90, and “z” is from 10 to 50. The CoxFeyBz is directly against the tunnel insulator. A non-magnetic region comprising an Os-containing material is between the two spaced magnetic regions. The other magnetic region comprises a magnetic Co-containing material. Other embodiments are disclosed.
    Type: Application
    Filed: June 7, 2019
    Publication date: October 3, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Wei Chen, Witold Kula, Manzar Siddik, Suresh Ramarajan, Jonathan D. Harms
  • Patent number: 10374149
    Abstract: A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material, a conductive second magnetic electrode spaced from the first electrode and comprising magnetic reference material, and a non-magnetic tunnel insulator material between the first and second electrodes. The magnetic reference material of the second electrode comprises a synthetic antiferromagnetic construction comprising two spaced magnetic regions one of which is closer to the tunnel insulator material than is the other. The one magnetic region comprises a polarizer region comprising CoxFeyBz where “x” is from 0 to 90, “y” is from 10 to 90, and “z” is from 10 to 50. The CoxFeyBz is directly against the tunnel insulator. A non-magnetic region comprising an Os-containing material is between the two spaced magnetic regions. The other magnetic region comprises a magnetic Co-containing material. Other embodiments are disclosed.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Wei Chen, Witold Kula, Manzar Siddik, Suresh Ramarajan, Jonathan D. Harms
  • Publication number: 20190206727
    Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material.
    Type: Application
    Filed: October 26, 2018
    Publication date: July 4, 2019
    Inventors: John B. Matovu, David S. Meyaard, Gowrisankar Damarla, Sri Sai Sivakumar Vegunta, Kunal Shrotri, Shashank Saraf, Kevin R. Gast, Jivaan Kishore Jhothiraman, Suresh Ramarajan, Lifang Xu, Rithu K. Bhonsle, Rutuparna Narulkar, Matthew J. King
  • Patent number: 10269625
    Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: April 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: John B. Matovu, David S. Meyaard, Gowrisankar Damarla, Sri Sai Sivakumar Vegunta, Kunal Shrotri, Shashank Saraf, Kevin R. Gast, Jivaan Kishore Jhothiraman, Suresh Ramarajan, Lifang Xu, Rithu K. Bhonsle, Rutuparna Narulkar, Matthew J. King
  • Publication number: 20180294403
    Abstract: A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material, a conductive second magnetic electrode spaced from the first electrode and comprising magnetic reference material, and a non-magnetic tunnel insulator material between the first and second electrodes. The magnetic reference material of the second electrode comprises a synthetic antiferromagnetic construction comprising two spaced magnetic regions one of which is closer to the tunnel insulator material than is the other. The one magnetic region comprises a polarizer region comprising CoxFeyBz where “x” is from 0 to 90, “y” is from 10 to 90, and “z” is from 10 to 50. The CoxFeyBz is directly against the tunnel insulator. A non-magnetic region comprising an Os-containing material is between the two spaced magnetic regions. The other magnetic region comprises a magnetic Co-containing material. Other embodiments are disclosed.
    Type: Application
    Filed: June 12, 2018
    Publication date: October 11, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Wei Chen, Witold Kula, Manzar Siddik, Suresh Ramarajan, Jonathan D. Harms
  • Patent number: 10062835
    Abstract: A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material, a conductive second magnetic electrode spaced from the first electrode and comprising magnetic reference material, and a non-magnetic tunnel insulator material between the first and second electrodes. The magnetic reference material of the second electrode comprises a synthetic antiferromagnetic construction comprising two spaced magnetic regions one of which is closer to the tunnel insulator material than is the other. The one magnetic region comprises a polarizer region comprising CoxFeyBz where “x” is from 0 to 90, “y” is from 10 to 90, and “z” is from 10 to 50. The CoxFeyBz is directly against the tunnel insulator. A non-magnetic region comprising an Os-containing material is between the two spaced magnetic regions. The other magnetic region comprises a magnetic Co-containing material. Other embodiments are disclosed.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: August 28, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Wei Chen, Witold Kula, Manzar Siddik, Suresh Ramarajan, Jonathan D. Harms
  • Publication number: 20170331032
    Abstract: A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material, a conductive second magnetic electrode spaced from the first electrode and comprising magnetic reference material, and a non-magnetic tunnel insulator material between the first and second electrodes. The magnetic reference material of the second electrode comprises a synthetic antiferromagnetic construction comprising two spaced magnetic regions one of which is closer to the tunnel insulator material than is the other. The one magnetic region comprises a polarizer region comprising CoxFeyBz where “x” is from 0 to 90, “y” is from 10 to 90, and “z” is from 10 to 50. The CoxFeyBz is directly against the tunnel insulator. A non-magnetic region comprising an Os-containing material is between the two spaced magnetic regions. The other magnetic region comprises a magnetic Co-containing material. Other embodiments are disclosed.
    Type: Application
    Filed: May 8, 2017
    Publication date: November 16, 2017
    Inventors: Wei Chen, Witold Kula, Manzar Siddik, Suresh Ramarajan, Jonathan D. Harms
  • Patent number: 9680089
    Abstract: A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material, a conductive second magnetic electrode spaced from the first electrode and comprising magnetic reference material, and a non-magnetic tunnel insulator material between the first and second electrodes. The magnetic reference material of the second electrode comprises a synthetic antiferromagnetic construction comprising two spaced magnetic regions one of which is closer to the tunnel insulator material than is the other. The one magnetic region comprises a polarizer region comprising CoxFeyBz where “x” is from 0 to 90, “y” is from 10 to 90, and “z” is from 10 to 50. The CoxFeyBz is directly against the tunnel insulator. A non-magnetic region comprising an Os-containing material is between the two spaced magnetic regions. The other magnetic region comprises a magnetic Co-containing material. Other embodiments are disclosed.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: June 13, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Wei Chen, Witold Kula, Manzar Siddik, Suresh Ramarajan, Jonathan D. Harms
  • Patent number: 9593431
    Abstract: Electroplating systems that include a plurality of electrodes, a power supply operably coupled to the plurality of electrodes, a platen for bearing a substrate on which metal features are to be formed, and an electrode support are disclosed. The electrode support may be configured for suspending the electrode assembly over an upper surface of the substrate disposed on the platen in spaced relation to and in alignment with the substrate or for supporting the electrode assembly in a stationary position over the substrate when the voltage is applied across the plurality of electrodes. The electrodes may be adjacent, mutually spaced and electrically isolated and connected in series so as to be oppositely polarized when the voltage is applied thereacross or may be connected so as to have alternating polarities when the voltage is applied thereacross.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: March 14, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Suresh Ramarajan, Whonchee Lee
  • Publication number: 20160211440
    Abstract: A semiconductor device comprises an array of magnetic cell structures each comprising a magnetic tunnel junction over an electrode on a substrate. Each of the magnetic tunnel junctions includes a magnetic material over the substrate, a first tunnel barrier material over the magnetic material, a second tunnel barrier material over the annealed first tunnel barrier material, and another magnetic material over the second tunnel barrier material. Each magnetic tunnel junction is configured to exhibit a tunnel magnetoresistance greater than or equal to about 180% at a resistance area product of less than about 8 ohm ?m2. The semiconductor device also includes another electrode over the another magnetic material. Semiconductor devices including the magnetic tunnel junctions, methods of forming the magnetic tunnel junctions, and methods of forming semiconductor devices including the magnetic tunnel junctions are disclosed.
    Type: Application
    Filed: January 15, 2015
    Publication date: July 21, 2016
    Inventors: Manzar Siddik, Witold Kula, Suresh Ramarajan
  • Publication number: 20130228458
    Abstract: Electroplating systems that include a plurality of electrodes, a power supply operably coupled to the plurality of electrodes, a platen for bearing a substrate on which metal features are to be formed, and an electrode support are disclosed. The electrode support may be configured for suspending the electrode assembly over an upper surface of the substrate disposed on the platen in spaced relation to and in alignment with the substrate or for supporting the electrode assembly in a stationary position over the substrate when the voltage is applied across the plurality of electrodes. The electrodes may be adjacent, mutually spaced and electrically isolated and connected in series so as to be oppositely polarized when the voltage is applied thereacross or may be connected so as to have alternating polarities when the voltage is applied thereacross.
    Type: Application
    Filed: April 16, 2013
    Publication date: September 5, 2013
    Applicant: Micron Technology, Inc.
    Inventors: Suresh Ramarajan, Whonchee Lee
  • Patent number: 8419906
    Abstract: Electroplating systems that include a plurality of electrodes, a power supply operably coupled to the plurality of electrodes, a platen for bearing a substrate on which metal features are to be formed, and an electrode support are disclosed. The electrode support may be configured for suspending the electrode assembly over an upper surface of the substrate disposed on the platen in spaced relation to and in alignment with the substrate or for supporting the electrode assembly in a stationary position over the substrate when the voltage is applied across the plurality of electrodes. The electrodes may be adjacent, mutually spaced and electrically isolated and connected in series so as to be oppositely polarized when the voltage is applied thereacross or may be connected so as to have alternating polarities when the voltage is applied thereacross.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: April 16, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Suresh Ramarajan, Whonchee Lee