Abstract: A nonvolatile semiconductor memory that reduces disturbing voltage to a non-selected memory cell during a write operation. The nonvolatile semiconductor memory according to exemplary embodiments of the present invention include a memory cell array, a word line control circuit, and a line control circuit. The memory cell array includes a plurality of memory cells provided in matrix form, a plurality of word lines, a plurality of bit lines, and a plurality of source lines. The word line control circuit controls the plurality of word lines. The line control circuit controls the plurality of bit lines and the plurality of source lines. Each of the memory cells includes a gate electrode coupled to the word lines, a first impurity region, a second impurity region, and an electron trap region provided in between the gate electrode and a substrate. The electron trap region is provided at least on the first impurity region side of the first impurity region side and the second impurity region side.

Abstract: A method for manufacturing the semiconductor device of which a transistor and a MNOS type memory transistor, each of which has a different gate withstand voltage and drain withstand voltage, are included in the same semiconductor layer.

Abstract: A semiconductor device having memory cells. Each of the memory cells has a word gate formed over a semiconductor substrate with a first gate insulating layer interposed, an impurity layer, and first and second control gates in the shape of sidewalls. The first and second control gates adjacent to each other with the impurity layer interposed are connected to a common contact section. The common contact section includes a first contact conductive layer, a second contact conductive layer, and a pad-shaped third contact conductive layer. The third contact conductive layer is formed over the first and second contact conductive layers.

Abstract: A fabrication method of a semiconductor device which has on the same semiconductor layer a transistor with a different high voltage gate as well as a high voltage drain and an MNOS memory transistor.

Abstract: A semiconductor device of the present invention has memory cells. Each of the memory cells includes a word gate formed over a semiconductor substrate with a first gate insulating layer interposed therebetween, an impurity layer, and first and second control gates in a shape of sidewalls. Each of the first and second control gates has a rectangular or square cross-sectional shape.

Abstract: A method of manufacturing a semiconductor device including a memory region in which non-volatile memory devices are arranged in a matrix form of a plurality of rows and a plurality of columns to form a memory cell array, the method including the steps of: forming a gate insulation layer, a conductive layer that will form a word gate, and a stopper layer above a semiconductor layer; forming a first insulation layer over the entire surface of the memory region; forming a first control gate in the form of a side wall on each of both side surfaces of the word gate, with the first insulation layer interposed with respect to the semiconductor layer; etching the surface of the first control gate; using that first control gate as a mask to remove part of the first insulation layer, thus forming a second insulation layer; forming a third conductive layer over the entire surface of the memory region; and forming a second control gate on the side surface of the first control gate, with the second insulation layer interp

Abstract: A semiconductor device having a memory region formed of non-volatile memory devices arranged in a matrix of a plurality of rows and columns. Each non-volatile memory device has a word gate formed above a semiconductor layer with a gate insulating layer interposed, an impurity layer formed in the semiconductor layer to form a source region or a drain region, and control gates formed in the form of side walls formed along both side surfaces of the word gate. Each control gate includes a first control gate and a second control gate in mutual contact, where the first and second control gates are respectively formed on charge accumulation layers of different thicknesses.

Abstract: On the production of bakery products using rice flour as a major material, the first object of the present invention is to provide a process for producing bakery products with improved qualities such as appearance, crumb, taste, and preservability, as well as satisfactory handleability. The second object of the present invention is to provide such bakery products having excellent qualities, which are obtainable thereby. The third object of the present invention is to provide premixed flours for producing the bakery products with improved qualities. The fourth object of the present invention is to provide fermented doughs for producing the excellent bakery products.

Abstract: A method of manufacturing a semiconductor device that has a high-breakdown-voltage transistor, a low-voltage driving transistor and a MONOS type memory transistor includes a step of forming a stack film that includes at least an oxide silicon layer and a nitride silicon layer over a high-breakdown-voltage transistor forming region where the high-breakdown-voltage transistor is formed, a low-voltage driving transistor forming region where the low-voltage driving transistor is formed and a MONOS type memory transistor forming region where the MONOS type memory transistor is formed in a semiconductor layer, a step of removing the stack film formed in a first gate insulating layer forming region of the high-breakdown-voltage transistor and a step of forming a first gate insulating layer in the high-breakdown-voltage transistor forming region by thermal oxidation.

Abstract: A fabrication method of a semiconductor device which has on the same semiconductor layer a transistor with a different high voltage gate as well as a high voltage drain and an MNOS memory transistor.

Abstract: A method for manufacturing the semiconductor device of which a transistor and a MNOS type memory transistor, each of which has a different gate withstand voltage and drain withstand voltage, are included in the same semiconductor layer.

Abstract: A method of manufacturing a semiconductor device includes: a step of forming a bottom oxide film on a silicon substrate in a memory transistor formation region and a peripheral circuit transistor formation region; a step of forming a nitride film on the bottom oxide film; a step of forming a top oxide film on the nitride film; a step of removing the top oxide film, the nitride film and the bottom oxide film from the peripheral circuit transistor formation region to expose a surface of the silicon substrate in the peripheral circuit transistor formation region; and a step of forming a gate oxide film on the silicon substrate in the peripheral circuit transistor formation region.

Abstract: A semiconductor device having memory cells. Each of the memory cells has a word gate formed over a semiconductor substrate with a first gate insulating layer interposed, an impurity layer, and first and second control gates in the shape of sidewalls. The first and second control gates adjacent to each other with the impurity layer interposed are connected to a common contact section. The common contact section includes a first contact conductive layer, a second contact conductive layer, and a pad-shaped third contact conductive layer. The third contact conductive layer is formed over the first and second contact conductive layers.

Abstract: To provide a nonvolatile semiconductor memory device in which a disturb voltage onto a non-selected memory cell in writing operation is lessened, a nonvolatile semiconductor memory device, includes: a memory cell array equipped with a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a plurality of source lines; a word line control circuit to control the plurality of word lines; and a line control circuit to control the plurality of bit lines and the plurality of source lines. Each of the plurality of memory cells is equipped with a gate electrode, a first impurity region, a second impurity region, and an electron trap region, which is positioned between the gate electrode and a substrate, and is formed at least at the first impurity region side of both the first impurity region and second impurity region.

Abstract: Exemplary embodiments of the present invention include nonvolatile semiconductor memory that reduces disturbing voltage to a non-selected memory cell during a write operation. The nonvolatile semiconductor memory according to exemplary embodiments of the present invention include a memory cell array, a word line control circuit, and a line control circuit. The memory cell array includes a plurality of memory cells provided in matrix form, a plurality of word lines, a plurality of bit lines, and a plurality of source lines. The word line control circuit controls the plurality of word lines. The line control circuit controls the plurality of bit lines and the plurality of source lines. Each of the memory cells includes a gate electrode coupled to the word lines, a first impurity region, a second impurity region, and an electron trap region provided in between the gate electrode and a substrate.

Abstract: When setting (changing) a reception mode in a receiving unit 40, a CPU 62 issues a reception mode command to the receiving unit 40. Having received the command, a serial interface 53 writes the command to a command buffer 52. A protocol controller 50 analyzes the command which has been written to the command buffer 52 to determine whether the reception mode is a FIX mode or an UNFIX mode, and writes a corresponding status (a device ID, unique ID, mode, etc.) to a status memory 54. Then, when data is received from a transmission unit 20, the receiving unit 40 refers to the status which has been written to determine whether or not the received data is from a transmission system which has been set.

Abstract: A semiconductor device having memory cells. Each of the memory cells has a word gate formed over a semiconductor substrate with a first gate insulating layer interposed, an impurity layer, and first and second control gates in the shape of sidewalls. The first and second control gates adjacent to each other with the impurity layer interposed are connected to a common contact section. The common contact section includes a first contact conductive layer, a second contact conductive layer, and a pad-shaped third contact conductive layer. The third contact conductive layer is formed over the first and second contact conductive layers.

Abstract: The manufacturing method of the present invention forms a patterned gate layer 140d as a dummy circuit on a peripheral portion of a chip 900 simultaneously with formation of a patterned gate layer 140a in a memory area 1000, prior to formation of an insulating layer 270 over whole surface of a semiconductor substrate. This causes appearance of a new protrusion on the top surface of the insulating layer 270 in the peripheral portion of the chip 900. The insulating layer 270 is subsequently polished by chemical mechanical polishing (CMP) technique. The presence of the new protrusion on the top surface of the insulating layer 270 effectively reduces the polishing rate and thereby decreases the polishing degree on the peripheral portion of the chip 900.

Abstract: A semiconductor device of the present invention includes memory cells. Each of the memory cells includes a word gate formed over a semiconductor substrate with a second gate insulating layer interposed therebetween, an impurity layer, and first and second control gates in the shape of sidewalls. The first and second control gates adjacent to the impurity layer interposed therebetween is connected with a common contact section. The common contact section includes a contact conductive layer, a stopper insulating layer, and a cap insulating layer. The contact conductive layer is continuous with the first and second control gates. The cap insulating layer is formed at least over the stopper insulating layer.

Abstract: A method of fabricating a semiconductor device in accordance with the present invention relates to a method of fabricating a semiconductor device including a memory region and a logic circuit region having a peripheral circuit, the method including the steps of: patterning a predetermined region formed of a stopper layer and a first conductive layer within the memory region, without patterning the logic circuit region; forming control gates in the form of side walls over both side surfaces of the first conductive layer within at least the memory region, with an ONO film interposed in between; forming first side wall dielectric layers on upper portions of the control gates; forming a gate electrode for a MOS transistor by patterning the first conductive layer within the logic circuit region; and forming a second side wall dielectric layer over the gate electrode and the side surfaces of the control gates and the first side wall dielectric layers.