Abstract: A storage control device provided with a plurality of channel control sections for receiving data input and output requests from an information processing device and transmitting and receiving data, to and from an information processing device, each of the plurality of channel control sections comprising: an input/output control section for receiving data input and output requests from the information processing device and controlling transmission and reception of data between a data storage memory and the information processing device; a processor; a data storage memory; and a data transfer device for transferring data in the data storage memory to a cache memory; and in a first channel control section of the plurality of channel control sections, the processor manages the data storage space in the data storage memory, and in a second channel control section, the input/output control section manages the data storage space in the data storage memory, and reports information relating to the data storage space

Abstract: The invention relates to a storage control device provided with a plurality of channel control sections for receiving data input and output requests from an information processing device and transmitting and receiving data, to and from an information processing device, each of the plurality of channel control sections comprising: an input/output control section for receiving data input and output requests from the information processing device and controlling transmission and reception of data between a data storage memory and the information processing device; a processor; a data storage memory; and a data transfer device for transferring data in the data storage memory to a cache memory; and in a first channel control section of the plurality of channel control sections, the processor manages the data storage space in the data storage memory, and in a second channel control section, the input/output control section manages the data storage space in the data storage memory, and reports information relating t

Abstract: A signal output section of a port sampling circuit 6 periodically changes the output level of an output port 11 based on a sampling period stored in a register which is set by CPU 2. A data latch section of the port sampling circuit 6 latches the data given to an input port 10 based on a timing signal, with a starting point being set on a change point of the output level. A data register stores the latched data.

Abstract: The present invention relates to a clock control circuit apparatus including a first oscillation circuit for generating a first clock signal and a second oscillation circuit for generating a second clock signal and capable of, when the two clock signals are put to use, improving the reliability of oscillation operations thereof. In the clock control circuit apparatus, a sub-clock correction unit corrects an oscillation frequency of a sub-clock signal on the basis of a main clock signal, while a main clock monitoring unit monitors an oscillation state of the main clock signal on the basis of the sub-clock signal.

Abstract: A signal output section of a port sampling circuit 6 periodically changes the output level of an output port 11 based on a sampling period stored in a register which is set by CPU 2. A data latch section of the port sampling circuit 6 latches the data given to an input port 10 based on a timing signal, with a starting point being set on a change point of the output level. A data register stores the latched data.

Abstract: In an integrated circuit in which function blocks constituting a CPU block, a memory block and the like, a power supply line for supplying power to the function blocks, and multiple signal lines for inputting and outputting signals to and from the function blocks are formed on a semiconductor substrate, bypass capacitors are provided on the power supply line in proximity to or inside the function blocks. The capacitances of these bypass capacitors are set in correspondence with the consumed current characteristics of the respective function blocks. As a result, noise produced on the power supply line by the operation of the function blocks can be suppressed and it is possible to certainly prevent such noise from leaking out through power supply terminals and input/output terminals of the integrated circuit to the outside.