Abstract: A battery control circuit having a battery voltage detecting section for detecting the voltage of a battery includes a resistor and a switching element which are connected in series and which are connected to the battery in parallel, and a battery controlling section for acquiring information relating to a change in the voltage of the battery, which is detected by the battery voltage detecting section, by turning on the switching element to allow a current of the battery to flow through the resistor. The battery controlling section determines the residual capacity of the battery based on the information relating to the change in the voltage of the battery.

Abstract: A sequential comparison type AD converter comprising series resistors for generating at respective connection portions reference values to convert an analog value to an m-bit digital value; a comparator for sequentially comparing the analog value and one of the reference value and outputting a digital value; a plurality of capacitive elements for distributing any one of the reference values by capacitance ratio; and a control unit for switching a value compared to the analog value by the comparator from a reference value to a distribution value of the plurality of capacitive elements when the comparator outputs an m-bit digital value, wherein the analog value is converted to an (m+n) bit digital value.

Abstract: A sequential comparison type AD converter comprising series resistors for generating at respective connection portions reference values to convert an analog value to an m-bit digital value; a comparator for sequentially comparing the analog value and one of the reference value and outputting a digital value; a plurality of capacitive elements for distributing any one of the reference values by capacitance ratio; and a control unit for switching a value compared to the analog value by the comparator from a reference value to a distribution value of the plurality of capacitive elements when the comparator outputs an m-bit digital value, wherein the analog value is converted to an (m+n) bit digital value.

Abstract: In a projection apparatus projecting an image by using light of a light source contained in a housing, there is provided a light source mounting device in which when the light source in the housing is replaced, the light source is mounted and the light source is raised from a position of an opening used for taking in and out a light source to a normal position to make positioning, so that the light source in the housing can be simply replaced.

Abstract: A USB device includes a key-input device for controlling data transfer. USB interfaces are provided with pipes for transferring data which connect endpoints severally provided in a personal computer and the USB device. Data transfer is performed through the pipes for transferring data in response to key-operated input information by the key-input device. Consequently, operations such as search and selection of a data file on the personal computer, start execution of data transfer and a halt of data transfer, can be performed not only by the personal computer but also by the device.

Abstract: A projection apparatus includes a prism holder for holding a synthesizing prism, the prism holder including a first positioning portion and being positioned and fixed to one end plane and the other end plane of the synthesizing prism opposite to each other, except for incidence planes of the synthesizing prism on which respective color light beams are incident and an outgoing plane of the synthesizing prism for outputting a synthesized light flux to the side of a projection optical unit, and a lens holder for holding the prism holder and a projection lens, the lens holder including a second positioning portion which is fitted to the first positioning portion of the prism holder to make positioning and fixing. Thus, assembling can be made with accuracy and without fail while positioning is made to the optical modulation element, the synthesizing prism, and the projection lens.

Abstract: A display apparatus and its cooling method in which the optical assemblies can be prevented from being smudged by dust entered into the apparatus so that an excellent image can be obtained and the apparatus can be cooled sufficiently with the apparatus including a housing having a screen on its front surface and a closed structure, an optical block having a closed structure and coupled with the housing in a closed fashion allowing air to circulate between the housing and the optical block. Further, the display apparatus includes a light source, a first cooling device for cooling the light source and a second cooling device for cooling the optical block. At least the optical block is arranged to have a closed structure and is cooled by air circulation.

Abstract: In a transporting vehicle provided with a trailer hauled by a tractor, the trailer is constructed by a first trailer unit connectable with the tractor and a second trailer unit detachably connectable with the first trailer unit. At mutually opposed connecting sections of the first and second trailer units is provided a connecting mechanism for integrally connecting the first and second trailer units with the rear end of the first trailer unit held in contact with the front end of the second trailer unit. The transporting vehicle can transport cargoes on roads other than main roads while being allowed to have a relatively simple construction and an improved loading capacity.

Abstract: In a display unit wherein an optical block is disposed inside of a housing having a screen at its front, and an image light from the optical block is projected on the screen, a display unit in which the housing is made a closed structure and a path is provided for circulating air between the housing and the optical block so that dust is prevented from entering inside of an apparatus and attaching to optical parts, and at the same time, heat generated in the apparatus can be sufficiently cooled.

Abstract: A microcomputer comprises: a first electric power source VDD1 to which a condenser 30 used for backup is added; a second electric power source VDD2 to which the condenser 30 used for backup is not added; and a resistance load 40 added to the second electric power source. When a supply of voltage of the second electric power source VDD2 is stopped, a level of the second electric power source VDD2 is changed from a high level to a low level, and when the supply of voltage of the second electric power source VDD2 is resumed, the level of the second electric power source VDD2 is returned from the low level to the high level.

Abstract: A hit-less cell switching device capable of switching ATM (Asynchronous Transfer Mode) cells between a system ZERO and a system ONE is disclosed. The system ZERO includes a first cell switch, a first input cell gate, a first output cell gate, and a first shaper. Likewise, the system ONE includes a second cell switch, a second input cell gate, a second output cell gate, and a second shaper. First, a controller opens the first and second input cell gates and first output cell gate, closes the second output cell gate, and puts the first and second cell switches and first and second shapers in a fully switched condition, thereby initializing the switching device. Subsequently, the controller closes the second input cell gate, evacuates queue buffers included in the second cell switch and second shaper, and opens the second output gate. After putting the two cell switches and two shapers in an in-switching state, the controller closes the first input cell gate and opens the second input cell gate simultaneously.

Abstract: A successive approximation AD converter is provided which can produce an (m+n)-bit digital signal having high AD conversion accuracy, by using a series resistor network having m-bit resolution. A successive approximation AD converter has: a switch 4 which switches a reference voltage from a series resistor network 1 either to be supplied to an input node of a comparator or not to be supplied to the input node; a switch group 7 consisting of an n number of switches which selectively connect an n number of capacitors of a capacitor group 8 to the input node 6 of the comparator 5; and a control circuit 9 which controls on/off operations of the switch 4 and the n number of switches of the switch group 7.

Abstract: A phase comparator compares the phase of a subject signal with that of a reference signal to produce a result therefrom. The subject signal is shifted in phase by &pgr;/4 and −&pgr;/4, separately. The two phase-shifted signals are respectively compared in phase with a reference signal. Resultant, two phase difference signals are applied to a decision circuit, which is operative on the basis of a rotary vector defined by the phase difference signals. The decision circuit determines the phase difference &agr; and whether the phase of the subject signal changes in one direction in which the phase differenece increases or in the opposite direction in which the difference decreases. A reversible counter is responsive to the decision circuit to increment or decrement its count accordingly. That allows the phase difference to be measured over many periods of the subject signals without requiring a frequency divider dividing the subject and reference signals.

Abstract: A basement unit comprises a reinforced concrete lower structural block having a floor portion and surrounding walls and at least one reinforced concrete upper structural block having surrounding walls and the same shape as the lower structural block in plan view. The upper structural block is stacked on top of the lower structural block with a seal member placed between the top end of the lower structural block and the bottom end of the upper structural block.

Abstract: A program for rewriting data in an address region B is written in an address region A which can be rewritten by an external PROM writer. After resetting the microcomputer and rewriting the program in address region A, the reset state is cancelled and the last address in address region A of the EEPROM (1) is then stored in a register (17). An address detector (18) prohibits rewriting in address region A based on an address value stored in the register (17).

Abstract: An EEPROM (1) is set to write mode when a program command to commence rewriting of data in region B in the EEPROM (1) is read out from region A. A CPU (2) then writes data specified by a latch (6) at an address in region B specified by a latch (4). In compliance with an inhibit signal INH, the CPU (2) now disregards the effects of the undefined output from the EEPROM (1) terminal DOUT.

Abstract: When data are to be written in an EEPROM (1), a CPU (2) sets a flag (12). A voltage booster (13) boosts the power voltage in compliance with the setting of the flag (12). A voltage boost detector (14) detects whether the output of the voltage booster (13) is in voltage boost state. If the output of the voltage booster (13) is not in voltage boost state, a latch (15) is reset and the EEPROM (1) is not permitted to switch to write mode. As a result, it is possible to prevent incorrect data writing in the EEPROM (1) even when the flag (12) has been incorrectly set.

Abstract: A method of an accurate detection of a spinning vehicle wheel. Observed wheel speeds are derived by measuring the speed of each wheel and the slowest speed is set as the slowest observed wheel speed. A maximum probable wheel speed is derived by multiplying the slowest observed wheel speed by the ratio of the maximum wheel speed to the slowest wheel speed for a given minimum turning radius. The maximum probable wheel speed is compared with an observed wheel speed and if the observed wheel speed is greater, the wheel is deemed to be spinning.

Abstract: A memory control circuit improves the read speed of a program memory stored in a ROM. The memory control circuit includes a memory divided into four blocks, an address translation circuit for providing address 4N+1 to blocks 0 and 1 only when the required read address is 4N+2 or 4N+3, a set of latch circuits for latching data read from each of the blocks, and a selector circuit for selecting necessary data from among the latched data and outputting it to a data bus. Accordingly, three or more blocks of memory are made readable in every latched operation.

Abstract: A method is provided to compute the probable body speed of a vehicle equipped with a mini tire as a spare tire, specifically when the mini tire is mounted. The wheel speeds of the four wheels are measured, and if the speed does not satisfy the predetermined formula relating to the wheel base and tread of the vehicle to a wheel speed, then a probable vehicle body speed is derived by the normal method. The speed thus derived is corrected by the diameter of the mini tire to compute a new probable vehicle body speed.