Patents by Inventor Susumu Yamada

Susumu Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5594888
    Abstract: The present invention is to improve the processing capability of a micro processor by speeding up a read operation of program memory stored in a ROM. The present invention comprises a first ROM for storing program data corresponding to even-numbered addresses and a second ROM for storing program data corresponding to odd-numbered addresses. It further comprises an address generator circuit for adding +1 to an address indicated by A1 - An when a least significant address bit A0 is 1. Hereby, when a present read operation is done for an odd-numbered address, an even-numbered address next to the foregoing odd-numbered address is simultaneously read to speed up read operation from a ROM.
    Type: Grant
    Filed: September 27, 1994
    Date of Patent: January 14, 1997
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Susumu Yamada
  • Patent number: 5500825
    Abstract: A plurality of delay time data can easily be obtained. A data input unit 32 successively writes data into a memory 30. A data output unit 36 outputs data from six areas a-f in the memory 30 in the parallel manner. Selection units SW1 and SW2 successively select and output data read out from the six areas a-f in the memory 30. Locations to be read are shifted from one another by the selection units SW1 and SW2 to output data from different memory locations. Thus, a plurality of data which are different in time between write and readout operations (i.e., different delay times) can be obtained simultaneously.
    Type: Grant
    Filed: June 28, 1994
    Date of Patent: March 19, 1996
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masato Onaya, Susumu Yamada
  • Patent number: 5347442
    Abstract: An electric power supply system used in electric trains or electric buses is equipped with a device for removing ripples of low frequencies which cause flickering in a lighting system on the train or bus. The system includes an inverter for inverting DC power to AC power, a low pass filter for passing components of the AC power having low frequencies, amplitude detecting means for detecting an amplitude of an output of the filter, error detecting means for detecting any deviation of the amplitude from a reference signal, and a control system for detecting and removing flickering components from an error signal generated by the error detecting means. The control system includes a flickering component passing device for passing only flickering components contained in an output of the filter, a phase compensating device for compensating a phase lag of the flickering components, and a gain compensating device for compensating a gain of the flickering components.
    Type: Grant
    Filed: May 8, 1992
    Date of Patent: September 13, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuma Henmi, Susumu Yamada
  • Patent number: 5329981
    Abstract: A method of producing a metal mold is disclosed. A heat resistant sheet is forcedly brought into close contact with a product configuration surface of a matrix such as a wooden pattern, a resin model, or the like by making use of negative pressure. The matrix is brought into contact with a melt of a low melting-point alloy while that state of close contact is being maintained and the melt is allowed to cool as it is, thereby casting one part of the mold which makes up a pair. The matrix is then removed, and by using the one part of the mold thus cast as a new matrix, this new matrix is brought into contact with the melt of a low melting-point alloy via the heat resistant rubber sheet and is allowed to cool as it is, thereby casting a counterpart of the mold that makes up the pair.
    Type: Grant
    Filed: October 7, 1993
    Date of Patent: July 19, 1994
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Masahito Ito, Miyuki Koujiya, Hiroshi Sarai, Seiya Nakao, Takao Nomura, Satoru Kitou, Fuminori Matsuda, Susumu Yamada, Kesato Kuroiwa, Hiroshi Mihara
  • Patent number: 5165099
    Abstract: The balance of the volumes in right and left channels in a stereo play back system is controlled. The amount of attenuation of an attenuator provided in each channel is controlled. When the levels of right and left stereo signals are judged to be approximately the same, an oscillator is permitted to oscillate and the pulses from the oscillator are counted by a counter. In accordance with a voltage signal which corresponds to the level ratio of the right and left stereo signals, whether the counter must count upwards or downwards is determined. The balance is controlled in accordance with the amount of attenuation of each attenuator which is determined in accordance with the decoded count value. The completion of the control is detected when the level ratio of the right and left stereo signals alternately change after they become substantially equal, and the control is automatically finished.
    Type: Grant
    Filed: June 26, 1991
    Date of Patent: November 17, 1992
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masato Onaya, Tsutomu Ishikawa, Susumu Yamada
  • Patent number: 4807020
    Abstract: Image reproduction condition data requisite for reproducing the images of plural originals are stored in a memory. In the system, certain of the data are automatically rad and set up to implement circuits which process image data successively for all the originals. A master processor communicates with intermediate processors. The implement circuits are controlled by subrodinate processors, which in turn are responsive to the intermediate processors or to the master processor. The system is further operable for accepting input of scanning condition data for one original while the system is reproducing an image of another original.
    Type: Grant
    Filed: July 13, 1984
    Date of Patent: February 21, 1989
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventors: Makoto Hirosawa, Susumu Yamada
  • Patent number: 4769275
    Abstract: A coated cloth, wherein a blend containing from 50 to 400 parts by weight of a hydroxide and more than 3 parts by weight of powdery fibers based on 100 parts by weight of a base polymer not containing halogen elements is coated on a cloth. The coated cloth is excellent in abrasion resistance and flame retardance, as well as releasing less smoke.
    Type: Grant
    Filed: February 17, 1987
    Date of Patent: September 6, 1988
    Assignee: Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Yutaka Inagaki, Susumu Yamada, Saburo Fukushima
  • Patent number: 4636870
    Abstract: A method and system for transforming images in reproducing images, in which image data obtained from original pictures are written into or read from a memory according to a specified transformation condition which is preliminarily given to a computer module to designate a scanning start point or start and stop points of each scanning line.
    Type: Grant
    Filed: December 6, 1983
    Date of Patent: January 13, 1987
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventors: Susumu Yamada, Mitsuhiko Yamada
  • Patent number: 4603456
    Abstract: Machining equipment for a production line using pallet type jigs, which includes a plurality of pallet type jigs, a conveyance line capable of conveying the jigs, a work bench provided on the conveyance line, a spindle head capable of being fed back and forth with respect to the work bench, and a control system for controlling the conveyance line, the work bench, and the spindle head. On the work bench are provided a horizontal rotary table which is capable of turning and indexing at a desired angle and has a constant turning position, and two rails which are rotatable coaxially and integrally with the horizontal rotary table and disposed side by side in the vertical direction to extend in the horizontal direction, in order to follow the alterations of the machining angle of a workpiece held by the pallet type jig and further to carry the pallet type jig in and out of the work bench conveniently.
    Type: Grant
    Filed: February 3, 1983
    Date of Patent: August 5, 1986
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Minoru Hiroyasu, Hitoshi Hashimoto, Susumu Yamada, Masaki Miyanaka, Hideharu Koizumi
  • Patent number: 4545706
    Abstract: A method and machine for machining the surface of a valve seat (3) which is required to have a very accurate alignment with respect to a guide bore of a valve guide (2).In order to be capable of machining the valve seat surface in high roundness while maintaining a high concentricity with the guide bore, a pilot member (4) is moved forward inclinably to catch a guide bore of a valve guide (2) at its front end; the pilot member is further moved forward bendably while following the guide bore; when the pilot member has reached the desired position, the posture of the pilot member in the position is firmly held; and the surface of the valve seat (3) is machined by moving edged tool members (5a) forwardly while rotating the edged tool members (5a) which are arranged coaxially with the pilot member.
    Type: Grant
    Filed: October 27, 1982
    Date of Patent: October 8, 1985
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Minoru Hiroyasu, Shigeru Yamagishi, Hideo Yamashita, Susumu Yamada, Koji Takahashi
  • Patent number: 4468607
    Abstract: A ladder-type signal attenuator comprises a ladder network (50) storing a ladder resistor circuit of a plurality of stages (n-1) each having an input resistor (2R) and an output resistor (R) and a ladder portion of the final stage (n) having an input resistor (8) and an output resistor (7) and coupled to the ladder resistor circuit. The resistance value (RB) of the input resistor (8) of the ladder portion of the final stage is different from 2R and/or the resistance value (RA) of the output resistor (7) is different from R. A bias voltage (Vb) or an analog input signal (Sin) is selectively applied to a corresponding signal input terminal of the ladder circuit (50) by means of switches (S.sub.1 to S.sub.n) in response to control data (b.sub.1 to b.sub.n) of n bits. At least one of the resistance values of the two resistors (7, 8) of the final stage ladder portion is changed as a function of the state "0" or "1" of the final bit (b.sub.
    Type: Grant
    Filed: May 4, 1982
    Date of Patent: August 28, 1984
    Assignees: Sanyo Electric Co., Ltd., Tokyo Sanyo Electric Co., Ltd.
    Inventors: Kouji Tanaka, Susumu Yamada