Abstract: An AD conversion circuit includes: a comparison unit that receives an analog signal and a reference signal, compares voltages of the signals, and outputs a first comparison signal; a signal generation unit that outputs a second comparison signal for switching a logic state, and outputs a third comparison signal that is a result of a logic operation on the first comparison signal and the second comparison signal; a control unit that outputs an enable signal; a clock generation unit that outputs first to nth clock signals having different phases; a latch unit that includes first to nth latch units, each of the first to nth latch units including an input terminal, a first control terminal, a second control terminal, and an output terminal, and latches a logic state of the one of the first to nth clock signals; and a count unit that performs a count operation.

Abstract: According to an embodiment, a storage device includes: a semiconductor memory that includes a multilevel memory cell, stores a first code word and a second code word, and in which a plurality of memory cells connected to one word line can store a plurality of pages; and a controller. The controller performs error correction processing of the first code word read out from one page among the plurality of pages of the semiconductor memory, and the second code word written in a page other than the page corresponding to the first code word among the plurality of pages, re-reads the first code word when the first code word is uncorrectable and the second code word was able to be corrected by the error correction processing, and determines a bit value of the first code word using a re-read result and the second code word after error correction.

Abstract: A solid-state imaging device is capable of suppressing as much as possible an increase in power consumption of a low-frequency noise removing process. A pixel unit includes pixels outputting pixel signals corresponding to an amount of incident light and correction pixels outputting correction pixel signals corresponding to a correction reference voltage. An AD conversion circuit includes a delay circuit, to which a plurality of delay elements are connected, and outputs a digital signal corresponding to the number of delay elements through which a pulse signal passes when the pulse signal passes through the number of delay elements corresponding to a level of the pixel signal or the correction pixel signal.

Abstract: In this solid-state imaging device, an output signal of any one of a plurality of delay units that output signals of logic states in accordance with a level of a pixel signal is input to an input terminal of a latch circuit that latches a logic state of the output signal. A NAND circuit and an INV circuit stop until a control signal output timing at which a control signal in accordance with the level of the pixel signal is output, and operate after the control signal output timing. A switch circuit outputs the output signal of the one of the plurality of delay units through a signal line from an output terminal until the control signal output timing, and switches a connection at a latch timing after a predetermined time elapses from the control signal output timing such that the NAND circuit and the INV circuit latch the logic state of the output signal of the one of the plurality of delay units.

Abstract: A memory controller includes a control unit configured to determine a storage location on a nonvolatile memory every unit data having a constant data length to be written into the nonvolatile memory, a plurality of parity storage units, an access control unit configured to select one parity storage unit on the basis of the storage location, and an XOR operation unit that performs an XOR operation every bit location by using the input unit data and data stored in the selected parity storage unit and stores an operation result of the XOR operation into the selected parity storage unit. Unit data is written into the nonvolatile memory. If the number of unit data which are input has reached a predetermined number, the operation result of the XOR operation stored in the parity storage unit is written into the nonvolatile memory.

Abstract: According to one embodiment, a storage control apparatus includes a first buffer controller and a second buffer controller. The first buffer controller is configured to store data of a first unit in each of data buffer regions, and the data of the first unit is transmitted from a host and written in a nonvolatile memory, or read from the nonvolatile memory and transmitted to the host. The second buffer controller is configured to independently transmit data of a second unit from the data buffer region corresponding to a bank prepared for transmission when data is written in the nonvolatile memory, and to independently transmit data of the second unit from a bank to be read to the data buffer region corresponding to the bank to be read when data is transmitted to the host.

Abstract: A solid-state imaging apparatus includes a pixel unit which has a plurality of pixels disposed in a two-dimensional matrix shape, wherein each of the pixels that a photoelectrical conversion element which generates a photoelectrical conversion signal corresponding to an amount of incident light disposed on a first substrate, and which outputs a photoelectrical conversion signal generated by each of the pixels to each row as a pixel signal, and an analog-to-digital converter which is disposed on every one or more columns of the pixel unit and generates a digital signal by digitizing a phase state of a multi-phase clock including clock signals of a plurality of phases different from each other at predetermined fixed intervals according to the pixel signal. Each of first and second circuit configuration units whose circuit scales are determined according to the multi-phase clock is disposed on a different substrate of a first or second substrate.

Abstract: In an A/D conversion circuit and a solid-state imaging device, a latch circuit is in a disable state until a first timing at which an output signal of a comparison unit has been inverted, and is in an enable state until a second timing at which a delay time of the inversion delay circuit has passed from the first timing. The latch circuit is in the enable state until the second timing according to comparison start in the comparison unit. The latch circuit latches an output signal of a delay unit at the second timing. A determination unit determines whether the latch circuit accurately latches the output signal of the delay unit, and outputs a signal indicating a determination result to a delay controller. The delay controller controls the delay time of the inversion delay circuit based on the determination result.

Abstract: A water jet propulsion boat includes a main chamber rib dividing the inside of an oil pan into a main chamber where an oil suction port of an oil suction tube is arranged, and an auxiliary chamber outside of the main chamber. The main chamber rib covers the oil suction port at least from the front side and from the left and right sides of the oil suction port. The main chamber rib projects upward from the floor of the oil pan. An opening through which oil passes is provided in the main chamber rib only rearward of a rear edge of the oil suction port. The main chamber and the auxiliary chamber communicate with each other through the opening.

Abstract: A clock generation circuit includes first and second logic circuits and a switch circuit. The first logic circuit has a first circuit threshold value lower than a circuit threshold value of a front-stage circuit, receives an input clock output from the front-stage circuit, and outputs a first output signal in accordance with a logic state of the input clock and the first circuit threshold value. The second logic circuit has a second circuit threshold value higher than the circuit threshold value of the front-stage circuit, receives the input clock output from the front-stage circuit, and outputs a second output signal in accordance with the logic state of the input clock and the second circuit threshold value. The switch circuit receives the first and second output signals and outputs, as an output clock, one of first and second voltages corresponding to different logic states.

Abstract: An AD conversion circuit includes: a comparison unit that receives an analog signal and a reference signal, compares voltages of the signals, and outputs a first comparison signal; a signal generation unit that outputs a second comparison signal for switching a logic state, and outputs a third comparison signal that is a result of a logic operation on the first comparison signal and the second comparison signal; a control unit that outputs an enable signal; a clock generation unit that outputs first to nth clock signals having different phases; a latch unit that includes first to nth latch units, each of the first to nth latch units including an input terminal, a first control terminal, a second control terminal, and an output terminal, and latches a logic state of the one of the first to nth clock signals; and a count unit that performs a count operation.

Abstract: According to one embodiment, a storage device includes a buffer memory, a write controller, a nonvolatile memory, and bank writing modules. Data buffer areas are set in the buffer memory. The write controller sequentially writes data transmitted from a host to the data buffer areas. Banks are set in the nonvolatile memory. The write controller writes data transmitted from the host to a data buffer area in the data buffer areas from which first data written to the data buffer area is read when one of the bank writing modules reads the first data. Each bank writing module reads second data from one of the data buffer areas independently of data write processing statuses of another bank writing module, and writes the second data to a corresponding bank.

Abstract: A shake detector includes: a shake detection unit that detects an amount of shake, and outputs a shake detection signal and a reference signal; a signal processing unit that amplifies and smoothes the shake detection signal and the reference signal, and outputs the shake detection signal as a signal used in subsequent processing; an adjustment unit that outputs an adjustment signal for adjusting an output signal from the signal processing unit; and a control operation unit that, in a first period for which there is no shake in the imaging apparatus, stores a control value for controlling the adjustment unit on the basis of the reference signal, and that, in a second period different from the first period, generates a control signal for controlling the adjustment unit on the basis of the reference signal and the stored control value and outputs the control signal.

Abstract: A solid state image pickup device may include a pixel unit that includes a plurality of pixels; a pulse delay unit that includes a plurality of delay elements, each of the plurality of delay elements including a power supply terminal; a stop control unit; a stop signal delay unit; a lower bit latch unit; a counter unit; a first upper bit latch unit; a second upper bit latch unit; and a correcting unit that compares an output signal of the first upper bit latch unit with an output signal of the second upper bit latch unit, and corrects a count value, which is a count result of the counter unit, based on a comparison result and an output signal of the lower bit latch unit.

Abstract: According to one embodiment, an image processing apparatus includes an extracted coordinates setting module, an image generator, and an output module. The extracted coordinates setting module sets extracted coordinates in a captured image along a direction in which a viewpoint moves with respect to an object in the captured image. The image generator sequentially extracts partial areas from the captured image in which perspective deformation of the object has been corrected based on the extracted coordinates, and generates a plurality of partial area images from the partial areas. The partial areas are in a size corresponding to the viewing angle of the human eye calculated according to an angle of view of the captured image. The output module outputs a moving image including the partial area images as frames.

Abstract: A clock generation circuit includes first and second logic circuits and a switch circuit. The first logic circuit has a first circuit threshold value lower than a circuit threshold value of a front-stage circuit, receives an input clock output from the front-stage circuit, and outputs a first output signal in accordance with a logic state of the input clock and the first circuit threshold value. The second logic circuit has a second circuit threshold value higher than the circuit threshold value of the front-stage circuit, receives the input clock output from the front-stage circuit, and outputs a second output signal in accordance with the logic state of the input clock and the second circuit threshold value. The switch circuit receives the first and second output signals and outputs, as an output clock, one of first and second voltages corresponding to different logic states.

Abstract: A water jet propulsion boat includes a main chamber rib dividing the inside of an oil pan into a main chamber where an oil suction port of an oil suction tube is arranged, and an auxiliary chamber outside of the main chamber. The main chamber rib covers the oil suction port at least from the front side and from the left and right sides of the oil suction port. The main chamber rib projects upward from the floor of the oil pan. An opening through which oil passes is provided in the main chamber rib only rearward of a rear edge of the oil suction port. The main chamber and the auxiliary chamber communicate with each other through the opening.

Abstract: A solid state image pickup device may include a pixel unit that includes a plurality of pixels; a pulse delay unit that includes a plurality of delay elements, each of the plurality of delay elements including a power supply terminal; a stop control unit; a stop signal delay unit; a lower bit latch unit; a counter unit; a first upper bit latch unit; a second upper bit latch unit; and a correcting unit that compares an output signal of the first upper bit latch unit with an output signal of the second upper bit latch unit, and corrects a count value, which is a count result of the counter unit, based on a comparison result and an output signal of the lower bit latch unit.

Abstract: A catalyst for purifying an exhaust gas can include a carrier having a honeycomb structure, an outer pipe for covering a part of the carrier, and a brazing foil for joining the outer peripheral surface of the carrier and the inner peripheral surface of the outer pipe on the downstream side of the catalyst. The catalyst can be fixed to a support flange such that an axial direction of the catalyst coincides with the direction in which an exhaust gas flows through an exhaust pipe. An upstream end of the brazing foil can be aligned with the upstream end of a catalyst fixing part of the support flange. An upstream end of the catalyst fixing part can be positioned upstream of the axial middle of the carrier. The brazing foil can be provided in a portion from the upstream end of the catalyst fixing part to the downstream side of the carrier. The catalyst can be supported at its generally middle part by the support flange.

Abstract: A polarization-independent SOA is provided which uses an InP substrate (11) as a semiconductor substrate and uses GaInNAs having introduced tensile strain as an active layer (14). With this configuration, the polarization independence is achieved by introducing the tensile strain, and high saturation optical output power is realized by reducing the film thickness of the active layer (14) as well as the gain peak wavelength is increased by reducing the band gap of the active layer (14) through use of GaInNAs made by adding nitrogen (N) to GaInAs as a material of the active layer (14) so as to achieve high gain especially in C-band and L-band even when band filling exits at the time of injecting a high current into the active layer (14).