Patents by Inventor Sven Beyer

Sven Beyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10319732
    Abstract: In sophisticated SOI transistor elements, the buried insulating layer may be specifically engineered so as to include non-standard dielectric materials. For instance, a charge-trapping material and/or a high-k dielectric material and/or a ferroelectric material may be incorporated into the buried insulating layer. In this manner, non-volatile storage transistor elements with superior performance may be obtained and/or efficiency of a back-bias mechanism may be improved.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: June 11, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Richter, Jochen Willi. Poth, Sven Beyer, Stefan Duenkel, Sandhya Chandrashekhar, Zhi-Yuan Wu
  • Patent number: 10283490
    Abstract: A method includes forming a stack of semiconductor die. The stack includes a first semiconductor die, a second semiconductor die and a third semiconductor die. The first semiconductor die is stacked above the second semiconductor die and the third semiconductor die is stacked above the first semiconductor die. A first optical transmitter and a first optical receiver are provided in the first semiconductor die, a second optical transmitter is provided in the second semiconductor die, and a second optical receiver is provided in the third semiconductor die. A first optical signal is transmitted from the first optical transmitter in the first semiconductor die to the second optical receiver in the third semiconductor die. A second optical signal is transmitted from the second optical transmitter in the second semiconductor die to the first optical receiver in the first semiconductor die.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: May 7, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Jan Hoentschel, Alexander Ebermann
  • Patent number: 10249633
    Abstract: An integrated circuit product includes a silicon-on-insulator (SOI) substrate and a flash memory device positioned in a first area of the SOI substrate. The SOI substrate includes a semiconductor bulk substrate, a buried insulating layer positioned above the semiconductor bulk substrate, and a semiconductor layer positioned above the buried insulating layer, and the flash memory device includes a flash transistor device and a read transistor device. The flash transistor device includes a floating gate, an insulating layer positioned above the floating gate, and a control gate positioned above the insulating layer, wherein the floating gate includes a portion of the semiconductor layer. The read transistor device includes a gate dielectric layer positioned above the semiconductor bulk substrate and a read gate electrode positioned above the gate dielectric layer.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: April 2, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Richter, Sven Beyer, Jan Paul
  • Patent number: 10163933
    Abstract: Methods of forming a buffer layer to imprint ferroelectric phase in a ferroelectric layer and the resulting devices are provided. Embodiments include forming a substrate; forming a buffer layer over the substrate; forming a ferroelectric layer over the buffer layer; forming a channel layer over the ferroelectric layer; forming a gate oxide layer over a portion of the channel layer; and forming a gate over the gate oxide layer.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ralf Richter, Stefan D√ľnkel, Martin Trentzsch, Sven Beyer
  • Publication number: 20180366484
    Abstract: In sophisticated SOI transistor elements, the buried insulating layer may be specifically engineered so as to include non-standard dielectric materials. For instance, a charge-trapping material and/or a high-k dielectric material and/or a ferroelectric material may be incorporated into the buried insulating layer. In this manner, non-volatile storage transistor elements with superior performance may be obtained and/or efficiency of a back-bias mechanism may be improved.
    Type: Application
    Filed: June 14, 2017
    Publication date: December 20, 2018
    Inventors: Ralf Richter, Jochen Willi. Poth, Sven Beyer, Stefan Duenkel, Sandhya Chandrashekhar, Zhi-Yuan Wu
  • Patent number: 10157996
    Abstract: A method includes forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor structure, the first material stack including a high-k material layer and a workfunction adjustment metal layer. The first material stack is patterned to remove a first portion of the first material stack from above the dummy gate region while leaving second portions of the first material stack above the first and second transistor regions. A gate electrode stack is formed above the first and second transistor regions and above the dummy gate region, and the gate electrode stack and the remaining second portions of the first material stack are patterned to form a first gate structure above the first transistor region, a second gate structure above the second transistor region, and a dummy gate structure above the dummy gate region.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: December 18, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Elliot John Smith, Jan Hoentschel, Nigel Chan, Sven Beyer
  • Patent number: 10084057
    Abstract: The present disclosure provides in one aspect a semiconductor device including a substrate structure comprising an active semiconductor material formed over a base substrate and a buried insulating material formed between the active semiconductor material and the base substrate, a ferroelectric gate structure disposed over the active semiconductor material in an active region of the substrate structure, the ferroelectric gate structure comprising a gate electrode and a ferroelectric material layer, and a contact region formed in the base substrate under the ferroelectric gate structure.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: September 25, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Martin Trentzsch, Stefan Flachowsky, Axel Henke
  • Patent number: 10033383
    Abstract: In illustrative embodiments disclosed herein, a logic element may be provided on the basis of a non-volatile storage mechanism, such as ferroelectric transistor elements, wherein the functional behavior may be adjusted or programmed on the basis of a shift of threshold voltages. To this end, a P-type transistor element and an N-type transistor element may be connected in parallel, while a ferroelectric material may be used so as to establish a first polarization state resulting in a first functional behavior and a second polarization state resulting in a second different functional behavior. For example, the logic element may enable a switching between P-type transistor behavior and N-type transistor behavior depending on the polarization state.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: July 24, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Richter, Stefan Duenkel, Sven Beyer
  • Publication number: 20180108668
    Abstract: An integrated circuit product includes a silicon-on-insulator (SOI) substrate and a flash memory device positioned in a first area of the SOI substrate. The SOI substrate includes a semiconductor bulk substrate, a buried insulating layer positioned above the semiconductor bulk substrate, and a semiconductor layer positioned above the buried insulating layer, and the flash memory device includes a flash transistor device and a read transistor device. The flash transistor device includes a floating gate, an insulating layer positioned above the floating gate, and a control gate positioned above the insulating layer, wherein the floating gate includes a portion of the semiconductor layer. The read transistor device includes a gate dielectric layer positioned above the semiconductor bulk substrate and a read gate electrode positioned above the gate dielectric layer.
    Type: Application
    Filed: December 5, 2017
    Publication date: April 19, 2018
    Inventors: Ralf Richter, Sven Beyer, Jan Paul
  • Publication number: 20180053832
    Abstract: The present disclosure provides in one aspect a semiconductor device including a substrate structure comprising an active semiconductor material formed over a base substrate and a buried insulating material formed between the active semiconductor material and the base substrate, a ferroelectric gate structure disposed over the active semiconductor material in an active region of the substrate structure, the ferroelectric gate structure comprising a gate electrode and a ferroelectric material layer, and a contact region formed in the base substrate under the ferroelectric gate structure.
    Type: Application
    Filed: August 16, 2016
    Publication date: February 22, 2018
    Inventors: Sven Beyer, Martin Trentzsch, Stefan Flachowsky, Axel Henke
  • Patent number: 9871050
    Abstract: A method of manufacturing a flash memory device is provided including providing a silicon-on-insulator (SOI) substrate, in particular, a fully depleted silicon-on-insulator (FDSOI) substrate, comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer and forming a memory device on the SOI substrate. Forming the flash memory device on the SOI substrate includes forming a flash transistor device and a read transistor device.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: January 16, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Richter, Sven Beyer, Jan Paul
  • Publication number: 20180012877
    Abstract: A method includes forming a stack of semiconductor die. The stack includes a first semiconductor die, a second semiconductor die and a third semiconductor die. The first semiconductor die is stacked above the second semiconductor die and the third semiconductor die is stacked above the first semiconductor die. A first optical transmitter and a first optical receiver are provided in the first semiconductor die, a second optical transmitter is provided in the second semiconductor die, and a second optical receiver is provided in the third semiconductor die. A first optical signal is transmitted from the first optical transmitter in the first semiconductor die to the second optical receiver in the third semiconductor die. A second optical signal is transmitted from the second optical transmitter in the second semiconductor die to the first optical receiver in the first semiconductor die.
    Type: Application
    Filed: September 22, 2017
    Publication date: January 11, 2018
    Inventors: Sven Beyer, Jan Hoentschel, Alexander Ebermann
  • Publication number: 20170345914
    Abstract: A method includes forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor structure, the first material stack including a high-k material layer and a workfunction adjustment metal layer. The first material stack is patterned to remove a first portion of the first material stack from above the dummy gate region while leaving second portions of the first material stack above the first and second transistor regions. A gate electrode stack is formed above the first and second transistor regions and above the dummy gate region, and the gate electrode stack and the remaining second portions of the first material stack are patterned to form a first gate structure above the first transistor region, a second gate structure above the second transistor region, and a dummy gate structure above the dummy gate region.
    Type: Application
    Filed: July 13, 2017
    Publication date: November 30, 2017
    Inventors: Elliot John Smith, Jan Hoentschel, Nigel Chan, Sven Beyer
  • Patent number: 9806067
    Abstract: A semiconductor die is provided with an optical transmitter configured to transmit an optical signal to another die and an optical receiver configured to receive an optical signal from another die. Furthermore, a method of forming a semiconductor device is provided including forming a first semiconductor die with the steps of providing a semiconductor substrate, forming a transistor device at least partially over the semiconductor substrate, forming an optical receiver one of at least partially over and at least partially in the semiconductor substrate, forming a metallization layer over the transistor device, and forming an optical transmitter one of at least partially over the metallization layer and at least partially in the metallization layer.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: October 31, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Jan Hoentschel, Alexander Ebermann
  • Patent number: 9793372
    Abstract: An integrated circuit includes a first transistor, a second transistor and a dummy gate structure. The first transistor includes a first gate structure. The first gate structure includes a first gate insulation layer including a high-k dielectric material and a first gate electrode. The second transistor includes a second gate structure. The second gate structure includes a second gate insulation layer including the high-k dielectric material and a second gate electrode. The dummy gate structure is arranged between the first transistor and the second transistor and substantially does not include the high-k dielectric material.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: October 17, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Elliot John Smith, Jan Hoentschel, Nigel Chan, Sven Beyer
  • Patent number: 9754951
    Abstract: A method of manufacturing a semiconductor device is provided which includes providing a semiconductor layer having a first area and a second area separated from the first area by an isolation structure, forming a protection layer on the isolation structure, forming at least partly a memory device in and on the first area, removing the protection layer, and forming a field effect transistor (FET) in and over the second area after the removal of the protection layer.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: September 5, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Richter, Sven Beyer
  • Patent number: 9711513
    Abstract: A semiconductor structure includes a nonvolatile memory cell including a source region, a channel region and a drain region that are provided in a semiconductor material. The channel region includes a first portion adjacent the source region and a second portion between the first portion of the channel region and the drain region. An electrically insulating floating gate is provided over the first portion of the channel region. The nonvolatile memory cell further includes a select gate and a control gate. The first portion of the select gate is provided over the second portion of the channel region. The second portion of the select gate is provided over a portion of the floating gate that is adjacent to the first portion of the select gate. The control gate is provided over the floating gate and adjacent to the second portion of the select gate.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: July 18, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Alban Zaka, Sven Beyer, Tom Herrmann, El Mehdi Bazizi
  • Patent number: 9698179
    Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a capacitor structure comprising an active region formed in a semiconductor substrate, a MOSFET device comprising source and drain regions formed in the active region and a gate electrode formed above the active region, and a first electrode and a second electrode formed in a metallization layer above the MOSFET device, wherein the first electrode is electrically connected with the source and drain regions via respective source and drain contacts and the second electrode is electrically connected with the gate electrode via a gate contact.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: July 4, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Elliot John Smith, Sven Beyer, Jan Hoentschel, Alexander Ebermann
  • Publication number: 20170125432
    Abstract: A method of manufacturing a semiconductor device is provided which includes providing a semiconductor layer having a first area and a second area separated from the first area by an isolation structure, forming a protection layer on the isolation structure, forming at least partly a memory device in and on the first area, removing the protection layer, and forming a field effect transistor (FET) in and over the second area after the removal of the protection layer.
    Type: Application
    Filed: December 29, 2015
    Publication date: May 4, 2017
    Inventors: Ralf Richter, Sven Beyer
  • Patent number: 9608112
    Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a method of forming a semiconductor device, the method including providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming a gate structure on the active semiconductor layer in an active region of the SOI substrate, partially exposing the base substrate for forming at least one bulk exposed region after the gate structure is formed, and forming a contact structure for contacting the at least one bulk exposed region.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: March 28, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Elliot John Smith, Sven Beyer, Tom Hasche, Jan Hoentschel