Patents by Inventor Sven Beyer

Sven Beyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Maintaining integrity of a high-K gate stack by an offset spacer used to determine an offset of a strain-inducing semiconductor alloy
    Patent number: 8378432
    Abstract: In sophisticated transistor elements including a high-k gate metal stack, the integrity of the sensitive gate materials may be ensured by a spacer element that may be concurrently used as an offset spacer for defining a lateral offset of a strain-inducing semiconductor alloy. The cap material of the sophisticated gate stack may be removed without compromising integrity of the offset spacer by providing a sacrificial spacer element. Consequently, an efficient strain-inducing mechanism may be obtained in combination with the provision of a sophisticated gate stack with the required material integrity, while reducing overall process complexity compared to conventional strategies.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: February 19, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Richard Carter, Sven Beyer, Martin Trentzsch
  • HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY EARLY CAP LAYER ADAPTATION
    Publication number: 20130034942
    Abstract: When forming high-k metal gate electrode structures in transistors of different conductivity type while also incorporating an embedded strain-inducing semiconductor alloy selectively in one type of transistor, superior process uniformity may be accomplished by selectively reducing the thickness of a dielectric cap material of a gate layer stack above the active region of transistors which do not receive the strain-inducing semiconductor alloy. In this case, superior confinement and thus integrity of sensitive gate materials may be accomplished in process strategies in which the sophisticated high-k metal gate electrode structures are formed in an early manufacturing stage, while, in a replacement gate approach, superior process uniformity is achieved upon exposing the surface of a placeholder electrode material.
    Type: Application
    Filed: August 3, 2012
    Publication date: February 7, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Rohit Pal, Sven Beyer, Andy Wei, Richard Carter
  • Method for forming CMOS transistors having metal-containing gate electrodes formed on a high-K gate dielectric material
    Patent number: 8367495
    Abstract: During the formation of sophisticated gate electrode structures, a replacement gate approach may be applied in which plasma assisted etch processes may be avoided. To this end, one of the gate electrode structures may receive an intermediate etch stop liner, which may allow the replacement of the placeholder material and the adjustment of the work function in a later manufacturing stage. The intermediate etch stop liner may not negatively affect the gate patterning sequence.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: February 5, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Markus Lenski, Richard Carter, Klaus Hempel
  • Work function adjustment in high-k gate stacks for devices of different threshold voltage
    Patent number: 8357604
    Abstract: In sophisticated semiconductor devices, different threshold voltage levels for transistors may be set in an early manufacturing stage, i.e., prior to patterning the gate electrode structures, by using multiple diffusion processes and/or gate dielectric materials. In this manner, substantially the same gate layer stacks, i.e., the same electrode materials and the same dielectric cap materials, may be used, thereby providing superior patterning uniformity when applying sophisticated etch strategies.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: January 22, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Sven Beyer, Thilo Scheiper
  • Equivalence verification between transaction level models and RTL at the example to processors
    Patent number: 8359561
    Abstract: A method for formally verifying the equivalence of an architecture description with an implementation description. The method comprises the steps of reading an implementation description, reading an architecture description, demonstrating that during execution of a same program with same initial values an architecture sequence of data transfers described by the architecture description is mappable to an implementation sequence of data transfers implemented by the implementation description, such that the mapping is bijective and ensures that the temporal order of the architecture sequence of data transfers corresponds to the temporal order of the implementation sequence of data transfers, and outputting a result of the verification of the equivalence of the architecture description with the implementation description.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: January 22, 2013
    Assignee: Onespin Solutions GmbH
    Inventors: Joerg Bormann, Sven Beyer, Sebastian Skalberg
  • Work function adjustment in a high-k gate electrode structure after transistor fabrication by using lanthanum
    Patent number: 8343837
    Abstract: The work function of a high-k gate electrode structure may be adjusted in a late manufacturing stage on the basis of a lanthanum species in an N-channel transistor, thereby obtaining the desired high work function in combination with a typical conductive barrier material, such as titanium nitride. For this purpose, in some illustrative embodiments, the lanthanum species may be formed directly on the previously provided metal-containing electrode material, while an efficient barrier material may be provided in the P-channel transistor, thereby avoiding undue interaction of the lanthanum species in the P-channel transistor.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: January 1, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Richard Carter, Sven Beyer, Joachim Metzger, Robert Binder
  • Increased depth of drain and source regions in complementary transistors by forming a deep drain and source region prior to a cavity etch
    Patent number: 8338894
    Abstract: Deep drain and source regions of an N-channel transistor may be formed through corresponding cavities, which may be formed together with cavities of a P-channel transistor, wherein the lateral offsets of the cavities may be adjusted on the basis of an appropriate reverse spacer regime. Consequently, the dopant species in the N-channel transistor extends down to a specific depth, for instance down to the buried insulating layer of an SOI device, while at the same time providing an efficient strain-inducing mechanism for the P-channel transistor with a highly efficient overall manufacturing process flow.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: December 25, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel, Sven Beyer
  • Strain memorization in strained SOI substrates of semiconductor devices
    Patent number: 8329531
    Abstract: In sophisticated semiconductor devices, the initial strain component of a globally strained semiconductor layer may be substantially preserved during the formation of shallow trench isolations by using a rigid mask material, which may efficiently avoid or reduce a deformation of the semiconductor islands upon patterning the isolation trenches. Consequently, selected regions with high internal stress levels may be provided, irrespective of the height-to-length aspect ratio, which may limit the application of globally strained semiconductor layers in conventional approaches. Furthermore, in some illustrative embodiments, active regions of substantially relaxed strain state or of inverse strain type may be provided in addition to the highly strained active regions, thereby enabling an efficient process strategy for forming complementary transistors.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: December 11, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Sven Beyer, Uwe Griebenow, Thilo Scheiper
  • Enhancing integrity of a high-k gate stack by protecting a liner at the gate bottom during gate head exposure
    Patent number: 8329549
    Abstract: Sophisticated gate stacks including a high-k dielectric material and a metal-containing electrode material may be covered by a protection liner, such as a silicon nitride liner, which may be maintained throughout the entire manufacturing sequence at the bottom of the gate stacks. For this purpose, a mask material may be applied prior to removing cap materials and spacer layers that may be used for encapsulating the gate stacks during the selective epitaxial growth of a strain-inducing semiconductor alloy. Consequently, enhanced integrity may be maintained throughout the entire manufacturing sequence, while at the same time one or more lithography processes may be avoided.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: December 11, 2012
    Assignee: Advanced Micro Devices Inc.
    Inventors: Sven Beyer, Frank Seliger, Gunter Grasshoff
  • Performance enhancement in transistors comprising high-k metal gate stack by an early extension implantation
    Patent number: 8318564
    Abstract: In sophisticated transistor elements, integrity of sensitive gate materials may be enhanced while, at the same time, the lateral offset of extension regions may be reduced. To this end, at least a portion of the extension regions may be implanted at an early manufacturing stage, i.e., in the presence of a protective liner material, which may, after forming the extension regions, be patterned into a protective spacer structure used for preserving integrity of the sensitive gate electrode structure.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: November 27, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Sven Beyer, Jan Hoentschel, Uwe Griebenow
  • Contacts and vias of a semiconductor device formed by a hard mask and double exposure
    Patent number: 8318598
    Abstract: A contact element may be formed on the basis of a hard mask, which may be patterned on the basis of a first resist mask and on the basis of a second resist mask, to define an appropriate intersection area which may represent the final design dimensions of the contact element. Consequently, each of the resist masks may be formed on the basis of a photolithography process with less restrictive constraints, since at least one of the lateral dimensions may be selected as a non-critical dimension in each of the two resist masks.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: November 27, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sven Beyer, Kai Frohberg, Katrin Reiche, Kerstin Ruttloff
  • Dual Cavity Etch for Embedded Stressor Regions
    Publication number: 20120292637
    Abstract: Generally, the present disclosure is directed to methods for forming embedded stressor regions in semiconductor devices such as transistor elements and the like. One illustrative method disclosed herein includes forming a first material in first cavities formed in a first active area adjacent to a first channel region of a semiconductor device, wherein the first material induces a first stress in the first channel region. The method also includes, among other things, forming a second material in second cavities formed in a second active area adjacent to a second channel region of the semiconductor device, wherein the second material induces a second stress in the second channel region that is of an opposite type of the first stress in the first channel region, and wherein the first and second cavities are formed during a common etch process.
    Type: Application
    Filed: May 17, 2011
    Publication date: November 22, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Sven Beyer, Peter Baars, Jan Hoentschel, Thilo Scheiper
  • Method of Forming Spacers That Provide Enhanced Protection for Gate Electrode Structures
    Publication number: 20120292671
    Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming a gate electrode structure above a semiconducting substrate and forming a plurality of spacers proximate the gate electrode structures, wherein the plurality of spacers comprises a first silicon nitride spacer positioned adjacent a sidewall of the gate electrode structure, a generally L-shaped silicon nitride spacer positioned adjacent the first silicon nitride spacer, and a silicon dioxide spacer positioned adjacent the generally L-shaped silicon nitride spacer.
    Type: Application
    Filed: May 16, 2011
    Publication date: November 22, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Peter Baars, Sven Beyer, Jan Hoentschel, Thilo Scheiper
  • SHORT CHANNEL TRANSISTOR WITH REDUCED LENGTH VARIATION BY USING AMORPHOUS ELECTRODE MATERIAL DURING IMPLANTATION
    Publication number: 20120280277
    Abstract: In sophisticated transistor elements, enhanced profile uniformity along the transistor width direction may be accomplished by using a gate material in an amorphous state, thereby reducing channeling effects and line edge roughness. In sophisticated high-k metal gate approaches, an appropriate sequence may be applied to avoid a change of the amorphous state prior to performing the critical implantation processes for forming drain and source extension regions and halo regions.
    Type: Application
    Filed: July 12, 2012
    Publication date: November 8, 2012
    Inventors: Thilo Scheiper, Andy Wei, Sven Beyer
  • Semiconductor device comprising a metal gate stack of reduced height and method of forming the same
    Patent number: 8293610
    Abstract: By providing a CMP stop layer in a metal gate stack, the initial height thereof may be efficiently reduced after the definition of the deep drain and source areas, thereby providing enhanced process conditions for forming highly stressed dielectric materials. Consequently, the dielectric material may be positioned more closely to the channel region substantially without deteriorating gate conductivity.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: October 23, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Rolf Stephan, Martin Trentzsch, Patrick Press
  • HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY SEPARATE REMOVAL OF PLACEHOLDER MATERIALS USING A MASKING REGIME PRIOR TO GATE PATTERNING
    Publication number: 20120261765
    Abstract: In a replacement gate approach in sophisticated semiconductor devices, the placeholder material of gate electrode structures of different type are separately removed. Furthermore, electrode metal may be selectively formed in the resulting gate opening, thereby providing superior process conditions in adjusting a respective work function of gate electrode structures of different type. In one illustrative embodiment, the separate forming of gate openings in gate electrode structures of different type may be based on a mask material that is provided in a gate layer stack.
    Type: Application
    Filed: June 26, 2012
    Publication date: October 18, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Sven Beyer, Klaus Hempel, Thilo Scheiper, Stefanie Steiner
  • Enhanced etch stop capability during patterning of silicon nitride including layer stacks by providing a chemically formed oxide layer during semiconductor processing
    Patent number: 8283232
    Abstract: A gate electrode structure may be formed on the basis of a silicon nitride cap material in combination with a very thin yet uniform silicon oxide based etch stop material, which may be formed on the basis of a chemically driven oxidation process. Due to the reduced thickness, a pronounced material erosion, for instance, during a wet chemical cleaning process after gate patterning, may be avoided, thereby not unduly affecting the further processing, for instance with respect to forming an embedded strain-inducing semiconductor alloy, while nevertheless providing the desired etch stop capabilities during removing the silicon nitride cap material.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: October 9, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Berthold Reimer, Falk Graetsch
  • Superior Integrity of High-K Metal Gate Stacks by Capping STI Regions
    Publication number: 20120223407
    Abstract: When forming high-k metal gate electrode structures in an early manufacturing stage, integrity of an encapsulation and, thus, integrity of sensitive gate materials may be improved by reducing the surface topography of the isolation regions. To this end, a dielectric cap layer of superior etch resistivity is provided in combination with the conventional silicon dioxide material.
    Type: Application
    Filed: February 28, 2012
    Publication date: September 6, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Thilo Scheiper, Peter Baars, Sven Beyer
  • Strain engineering in three-dimensional transistors based on globally strained semiconductor base layers
    Patent number: 8247275
    Abstract: Non-planar transistors, such as FINFETs, may be formed on the basis of a globally strained semiconductor material, thereby preserving a high uniaxial strain component in the resulting semiconductor fins. In this manner, a significant performance enhancement may be achieved without adding process complexity when implementing FINFET transistors.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: August 21, 2012
    Assignee: GlobalFoundries, Inc.
    Inventors: Jan Hoentschel, Sven Beyer, Uwe Griebenow
  • Short channel transistor with reduced length variation by using amorphous electrode material during implantation
    Patent number: 8241977
    Abstract: In sophisticated transistor elements, enhanced profile uniformity along the transistor width direction may be accomplished by using a gate material in an amorphous state, thereby reducing channeling effects and line edge roughness. In sophisticated high-k metal gate approaches, an appropriate sequence may be applied to avoid a change of the amorphous state prior to performing the critical implantation processes for forming drain and source extension regions and halo regions.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: August 14, 2012
    Assignee: GlobalFoundries Inc.
    Inventors: Thilo Scheiper, Andy Wei, Sven Beyer