Abstract: System and method for configuring via meshes for a semiconductor circuit having at least a bottom layer and a top layer each having a plurality of parallel conductive straps, and vias to interconnect straps in the bottom layer to the top layer to provide conductive routing pathways is disclosed. The method and system include inputting predefined criteria for the via mesh, and configuring feasible straps in the bottom layer of straps using a set of predefined rules and configuring feasible straps for the top layer, and optionally the intermediate layers using the set of predefined rules. The predefined criteria preferably includes one or all of: defining the bottom and top layer connection locations, defining a set of predefined tracks for each layer, defining the number of layers and straps in each layer, and combinations thereof.

Abstract: Systems and methods to perform integrated circuit development include identifying one or more multi-sink nets in a design of the integrated circuit. Each of the one or more multi-sink nets includes a source that supplies signals to two or more sinks. A method includes determining a wire tag for each of the two or more sinks of each of the one or more multi-sink nets. Each wire tag defines characteristics of a wire connecting the source to the sink, and the characteristics include a wire width and a range of metal layers within the integrated circuit for traversal of the wire. The method also includes providing the design and the wire tags for fabrication of the integrated circuit.

Abstract: Systems and methods to perform integrated circuit development include identifying one or more multi-sink nets in a design of the integrated circuit. Each of the one or more multi-sink nets includes a source that supplies signals to two or more sinks. A method includes determining a wire tag for each of the two or more sinks of each of the one or more multi-sink nets. Each wire tag defines characteristics of a wire connecting the source to the sink, and the characteristics include a wire width and a range of metal layers within the integrated circuit for traversal of the wire. The method also includes providing the design and the wire tags for fabrication of the integrated circuit.

Abstract: System and method for configuring via meshes for a semiconductor circuit having at least a bottom layer and a top layer each having a plurality of parallel conductive straps, and vias to interconnect straps in the bottom layer to the top layer to provide conductive routing pathways is disclosed. The method and system include inputting predefined criteria for the via mesh, and configuring feasible straps in the bottom layer of straps using a set of predefined rules and configuring feasible straps for the top layer, and optionally the intermediate layers using the set of predefined rules. The predefined criteria preferably includes one or all of: defining the bottom and top layer connection locations, defining a set of predefined tracks for each layer, defining the number of layers and straps in each layer, and combinations thereof.

Abstract: Embodiments of the invention include method, systems and computer program products for creating a circuit design using a generated tree. The computer-implemented method includes receiving, by one or more processors, a design area for a microelectronic device, wherein the design area includes a plurality of sub-units, each sub-unit from the plurality of sub-units capable of receiving a control signal. The processor determines a location of a source and one or more sinks within the design area. The processor further calculates a center of gravity (COG) based on the location of the one or more sinks. The processor connects the COG to each of the one or more sinks. The processor further connects the COG to the source.

Abstract: System and method for configuring via meshes for a semiconductor circuit having at least a bottom layer and a top layer each having a plurality of parallel conductive straps, and vias to interconnect straps in the bottom layer to the top layer to provide conductive routing pathways is disclosed. The method and system include inputting predefined criteria for the via mesh, and configuring feasible straps in the bottom layer of straps using a set of predefined rules and configuring feasible straps for the top layer, and optionally the intermediate layers using the set of predefined rules. The predefined criteria preferably includes one or all of: defining the bottom and top layer connection locations, defining a set of predefined tracks for each layer, defining the number of layers and straps in each layer, and combinations thereof.

Abstract: System and method for configuring via meshes for a semiconductor circuit having at least a bottom layer and a top layer each having a plurality of parallel conductive straps, and vias to interconnect straps in the bottom layer to the top layer to provide conductive routing pathways is disclosed. The method and system include inputting predefined criteria for the via mesh, and configuring feasible straps in the bottom layer of straps using a set of predefined rules and configuring feasible straps for the top layer, and optionally the intermediate layers using the set of predefined rules. The predefined criteria preferably includes one or all of: defining the bottom and top layer connection locations, defining a set of predefined tracks for each layer, defining the number of layers and straps in each layer, and combinations thereof.

Abstract: A method can include receiving design data of the integrated circuit, the design data indicates a set of sub-units partitioning an area of an integrated circuit, and a clock tree coupling the sub-units, the clock tree including a selected memory element, a predecessor memory element, and successor elements; determining a valid placement region for relocating the selected memory element; generating grid comprising first set of perpendicularly intersecting lines through the selected memory element, predecessor memory element, and successor elements; extending the grid to include second set of perpendicularly intersecting lines through vertices of the valid placement region and through intersections between edges of the valid placement region and the first set of perpendicularly intersecting lines; determining, within the valid placement region, a point in the extended grid having a minimum total rectilinear distance to the predecessor memory element and the successor elements; relocating the memory element to t

Abstract: A router is used to produce a first integrated circuit structure according to an engineering change order. An initial detail routing topology is imported for the first integrated circuit structure. An engineering change order is received instructing the router to change a portion of the initial detail routing topology for the first integrated circuit structure. A global routing operation is performed which routes global wires for the portion of the initial detail routing topology for the first integrated circuit structure. For each global wire which is routed, a specific global wiring track is selected for the global wire within each edge of a set of global tiles in a routing topology for the first integrated circuit.

Abstract: A routing specification is received for nets of an integrated circuit connecting source cells and sink cells in the integrated circuit. A target performance parameter is received for each of the nets, the target performance parameters specifying a propagation property of electrical signals in the nets. Layouts of the nets are generated according to the routing specification. An actual performance parameter for each of the nets in the layouts is generated, in which the actual performance parameters specify a calculated actual propagation property of electrical signals in the nets. A deviation parameter is generated for each of the performance parameters. Each of the deviation parameters is indicative of a degree of deviation of the respective actual performance parameter from its target performance parameter.

Abstract: A routing specification is received for nets of an integrated circuit connecting source cells and sink cells in the integrated circuit. A target performance parameter is received for each of the nets, the target performance parameters specifying a propagation property of electrical signals in the nets. Layouts of the nets are generated according to the routing specification. An actual performance parameter for each of the nets in the layouts is generated, in which the actual performance parameters specify a calculated actual propagation property of electrical signals in the nets. A deviation parameter is generated for each of the performance parameters. Each of the deviation parameters is indicative of a degree of deviation of the respective actual performance parameter from its target performance parameter.

Abstract: A method can include receiving design data of the integrated circuit, the design data indicates a set of sub-units partitioning an area of an integrated circuit, and a clock tree coupling the sub-units, the clock tree including a selected memory element, a predecessor memory element, and successor elements; determining a valid placement region for relocating the selected memory element; generating grid comprising first set of perpendicularly intersecting lines through the selected memory element, predecessor memory element, and successor elements; extending the grid to include second set of perpendicularly intersecting lines through vertices of the valid placement region and through intersections between edges of the valid placement region and the first set of perpendicularly intersecting lines; determining, within the valid placement region, a point in the extended grid having a minimum total rectilinear distance to the predecessor memory element and the successor elements; relocating the memory element to t

Abstract: According to an aspect, a method includes accessing an initial layout of global wires and a congestion related metric for each net in a gate level design description of an integrated circuit. A second layout is accessed that specifies, for each net, detailed routing information that includes connections between specific wires in the regions of the integrated circuit. A list of nets with a same source region and target region in the initial layout as the failing net is generated. A net in the list of nets is selected and the failing net is rerouted over the selected net. The rerouting includes the global router updating the initial layout and the detailed router updating the second layout. The congestion related metric for each net is updated in response to the global router updating the initial layout.

Abstract: The present disclosure relates to methods, processing systems and computer program products of global routing of integrated circuits based on localized routing optimization. In certain embodiments, the method may include one or more of: defining one or more regions, one or more netgroups, and combinations thereof of an integrated circuit, associating at least one optimization objective with each region and/or each netgroup defined, generating one or more constraints for each region and/or each netgroup based on the associated optimization objectives, and performing global routing of the integrated circuit according to the one or more constraints.

Abstract: A router is used to produce a first integrated circuit structure according to an engineering change order. An initial detail routing topology is imported for the first integrated circuit structure. An engineering change order is received instructing the router to change a portion of the initial detail routing topology for the first integrated circuit structure. A global routing operation is performed which routes global wires for the portion of the initial detail routing topology for the first integrated circuit structure. For each global wire which is routed, a specific global wiring track is selected for the global wire within each edge of a set of global tiles in a routing topology for the first integrated circuit.

Abstract: According to an aspect, a method includes accessing an initial layout of global wires and a congestion related metric for each net in a gate level design description of an integrated circuit. A second layout is accessed that specifies, for each net, detailed routing information that includes connections between specific wires in the regions of the integrated circuit. A list of nets with a same source region and target region in the initial layout as the failing net is generated. A net in the list of nets is selected and the failing net is rerouted over the selected net. The rerouting includes the global router updating the initial layout and the detailed router updating the second layout. The congestion related metric for each net is updated in response to the global router updating the initial layout.

Abstract: According to an aspect, a plurality of nets are grouped into a plurality of buckets based on timing criticalities associated with the nets, and different TCRs are assigned to each of the buckets. For each of the nets, a TCR for the net is determined based on the TCR assigned to the bucket containing the net. Global routing of the net is performed according to the TCR and to one or more constraints associated with the net. The TCR for the net is incremented by a specified amount in response to the global routing of the net resulting in violating at least one of the one or more constraints associated with the net and to a stopping criteria not being met. The performing global routing and incrementing the TCR for the net is repeated.

Abstract: According to an aspect, a plurality of nets are grouped into a plurality of buckets based on timing criticalities associated with the nets, and different TCRs are assigned to each of the buckets. For each of the nets, a TCR for the net is determined based on the TCR assigned to the bucket containing the net. Global routing of the net is performed according to the TCR and to one or more constraints associated with the net. The TCR for the net is incremented by a specified amount in response to the global routing of the net resulting in violating at least one of the one or more constraints associated with the net and to a stopping criteria not being met. The performing global routing and incrementing the TCR for the net is repeated.

Abstract: According to an aspect, a method includes accessing an initial layout of global wires and a congestion related metric for each net in a gate level design description of an integrated circuit. A second layout is accessed that specifies, for each net, detailed routing information that includes connections between specific wires in the regions of the integrated circuit. A list of nets with a same source region and target region in the initial layout as the failing net is generated. A net in the list of nets is selected and the failing net is rerouted over the selected net. The rerouting includes the global router updating the initial layout and the detailed router updating the second layout. The congestion related metric for each net is updated in response to the global router updating the initial layout.

Abstract: According to an aspect, a method includes accessing an initial layout of global wires and a congestion related metric for each net in a gate level design description of an integrated circuit. A second layout is accessed that specifies, for each net, detailed routing information that includes connections between specific wires in the regions of the integrated circuit. A list of nets with a same source region and target region in the initial layout as the failing net is generated. A net in the list of nets is selected and the failing net is rerouted over the selected net. The rerouting includes the global router updating the initial layout and the detailed router updating the second layout. The congestion related metric for each net is updated in response to the global router updating the initial layout.