Abstract: A port is to couple to another die over a die-to-die (D2D) link and includes a die-to-die (D2D) adapter to determine, from a set of registers, a set of capabilities of the D2D adapter to advertise in a negotiation with a link partner D2D adapter, where the D2D adapter is on a die and the link partner D2D adapter is located on a remote link partner die. A first capabilities advertisement message is sent to the link partner D2D adapter to advertise the set of capabilities to the link partner D2D adapter. A second capabilities advertisement message is received from the link partner D2D adapter, wherein the second capabilities advertisement message identifies a set of capabilities of the link partner D2D adapter. A final configuration of a D2D link is determined to couple the die to the link partner die.

Abstract: Embodiments herein relate to action that are to be taken on various lanes of a die-to-die (D2D) interconnect in the event of clock-gating. Specifically, based on identification that a clock-gating event is to occur, physical layer (PHY) logic may direct PHY electrical circuitry to set the state of various of the lanes. In some embodiments, different actions may be taken based on whether the D2D interconnect is terminated or unterminated. Other embodiments may be described and claimed.

Abstract: Systems, methods, and apparatuses can include transmission-side protocol stack circuitry comprising first cyclic redundancy check (CRC) circuitry to determine first CRC code for a first set of information and to determine second CRC code for a second set of information; and Flit encoding circuitry to encode a first portion of a Flit with the first set of information and the first CRC code, the Flit encoding circuitry to encode a second portion of the Flit with the second set of information and the second CRC code. Receiver-side protocol stack circuitry can include a low-latency path comprising first CRC check circuitry to perform a CRC check on a first portion of a received Flit. Receiver-side protocol stack circuitry can include a non-low-latency path comprising forward error correction (FEC) decoder circuitry to perform FEC on received Flits, and second CRC check circuitry to perform CRC check on received Flits that pass FEC.

Abstract: In one embodiment, an apparatus comprises a first die that includes: a die-to-die adapter comprising a plurality of first registers, the die-to-die adapter to communicate with protocol layer circuitry via a flit-aware die-to-die interface (FDI) and physical layer circuitry via a raw die-to-die interface (RDI), wherein the die-to-die adapter is to receive message information of a first interconnect protocol; and the physical layer circuitry coupled to the die-to-die adapter, the physical layer circuity comprising a plurality of second registers, where the physical layer circuitry is to receive and output the message information to a second die via an interconnect having a mainband and a sideband. During a test of the apparatus, the sideband is to enable access to information in at least one of the plurality of first registers or at least one of the plurality of second registers. Other embodiments are described and claimed.

Abstract: A port is to couple to another die over a die-to-die (D2D) link and includes physical layer (PHY) circuitry including a first number of sideband lanes to carry data for use in training and management of the D2D link, and a second number of mainband lanes to implement a main data path of the D2D link. The mainband lanes include a forwarded clock lane, a valid lane, and a plurality of data lanes. A logical PHY coordinates functions of the sideband lanes and the mainband lanes.

Abstract: A device includes a port with a replay buffer and protocol logic to receive a flit in a sequence of flits to be sent on a point-to-point link and determine an error in the flit. Based on the error, a copy of the flit is stored in a first position within the replay buffer as well as a copy of a next flit received in the sequence of flits, which is stored in a second position within the replay buffer. The copies of the flits are then written to a register for access by software.

Abstract: In one embodiment, an apparatus includes: a die-to-die adapter to communicate with protocol layer circuitry and physical layer circuitry; and the physical layer circuitry coupled to the die-to-die adapter, where the physical layer circuitry is to receive and output first information to a second die via an interconnect. The physical layer circuitry may include: a first sideband data receiver to couple to a first sideband data lane and a first sideband clock receiver to couple to a first sideband clock lane; and a second sideband data receiver to couple to a second sideband data lane and a second sideband clock receiver to couple to a second sideband clock lane. The physical layer circuitry may assign a functional sideband comprising: one of the first or second sideband data lanes; and one of the first or second sideband clock lanes. Other embodiments are described and claimed.

Abstract: A single communication fabric for a data processing apparatus is provided. The fabric has an interconnection network to provide a topology of data communication channels between a plurality of data-handling functional units. The interconnection network has a first interconnection domain to provide data communication between a first subset of the data-handling functional units and a second interconnection domain to provide data communication between a second subset of the data-handling functional units. The power management circuitry is arranged to control a first performance level for the first interconnection domain independently from control of a second performance level for the second interconnection domain. Machine readable instructions and a method are provided to concurrently set performance levels of two different fabric domains to respective different operating frequencies.

Abstract: A FEC codec for generating a check byte for a message. The FEC codec includes a port encoder having a storage unit, a Galois field multiplier, and a sum unit. The storage unit stores a first staged result, which is accumulated based on previous sets of input byte of the message for all clock cycles from a first clock cycle to a clock cycle immediately prior to the current clock cycle. The Galois field multiplier performs a Galois field multiplication of the first staged result and a power of the alpha to generate a Galois field product. The sum unit performs a Galois field addition on an internal input based on a consolidated byte for the current clock cycle and the Galois field product to generate a second staged result for subsequent use to generate the check byte. Other embodiments may be described and/or claimed.

Abstract: In one embodiment, an apparatus includes: a first link layer circuit to perform link layer functionality for a first communication protocol; and a logical physical (logPHY) circuit coupled to the first link layer circuit via a logical PHY interface (LPIF) link, the logPHY circuit to communicate with the first link layer circuit in a flit mode in which the first information is communicated in a fixed width size and to communicate with another link layer circuit in a non-flit mode. Other embodiments are described and claimed.

Abstract: An adapter is provided that includes a first interface to couple to a particular device, where link layer data is to be communicated over the first interface, and a second interface to couple to a physical layer (PHY) device. The PHY device includes wires to implement a physical layer of a link, and the link couples the adapter to another adapter via the PHY device. The second interface includes a data channel to communicate the link layer data over the physical layer, and a sideband channel to communicate sideband messages between the adapter and the other adapter over the physical layer. The adapter is to implement a logical PHY for the link.

Abstract: Systems, methods, and apparatuses can include transmission-side protocol stack circuitry comprising first cyclic redundancy check (CRC) circuitry to determine first CRC code for a first set of information and to determine second CRC code for a second set of information; and Flit encoding circuitry to encode a first portion of a Flit with the first set of information and the first CRC code, the Flit encoding circuitry to encode a second portion of the Flit with the second set of information and the second CRC code. Receiver-side protocol stack circuitry can include a low-latency path comprising first CRC check circuitry to perform a CRC check on a first portion of a received Flit. Receiver-side protocol stack circuitry can include a non-low-latency path comprising forward error correction (FEC) decoder circuitry to perform FEC on received Flits, and second CRC check circuitry to perform CRC check on received Flits that pass FEC.

Abstract: For example, an Integrated Circuit, e.g., a chiplet, may include Physical layer (PHY) circuitry to communicate with another IC, e.g., chiplet, over a Universal Chiplet Interconnect Express (UCIe) link. For example, the IC may include a System on Chip (SoC) bridge, which may be configured to transport a plurality of Management Transport Packets (MTPs) over a plurality of connection links of the UCIe link. For example, the SoC bridge may be configured to transport the plurality of MTPs according to a predefined interleaving scheme. For example, the predefined interleaving scheme may define a predefined order of assignment of a plurality of credit-path MTPs to a plurality of Receive (R×) Queue Identifiers (R×Q-IDs) corresponding to the plurality of connection links.

Abstract: An interface for coupling an agent to a fabric supports a set of coherent interconnect protocols and includes a global channel to communicate control signals to support the interface, a request channel to communicate messages associated with requests to other agents on the fabric, a response channel to communicate responses to other agents on the fabric, and a data channel to couple to communicate messages associated with data transfers to other agents on the fabric, where the data transfers include payload data.

Abstract: Technologies for a unified debug and test architecture in chiplets is disclosed. In an illustrative embodiment, several chiplets are integrated on an integrated circuit package. The chiplets are connected by a package interconnect, such as a universal chiplet interconnect express (UCIe) interconnect. Each chiplet includes several debug nodes, which are connected by an on-chiplet network. One of the chiplets, referred to as a package debug endpoint, acts as a link endpoint for an off-package link, such as a peripheral component interconnect express (PCIe) link. In use, debug messages can be sent to the package debug endpoint over a PCIe link. The debug messages can be routed within the chiplets and between chiplets, allowing for the debug functionality at each debug node to be probed using a common protocol. In this manner, chiplets from different vendors can be integrated into the same package and tested using common software.

Abstract: Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to on-package die-to-die (D2D) interconnects. Specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.

Abstract: In one embodiment, a fabric circuit is to receive requests for ownership and data commits from an agent. The fabric circuit includes a control circuit to maintain statistics regarding the requests for ownership and the data commits and throttle the fabric circuit based at least in part on the statistics. Other embodiments are described and claimed.

Abstract: An adapter is provided that includes a first interface to couple to a particular device, where link layer data is to be communicated over the first interface, and a second interface to couple to a physical layer (PHY) device. The PHY device includes wires to implement a physical layer of a link, and the link couples the adapter to another adapter via the PHY device. The second interface includes a data channel to communicate the link layer data over the physical layer, and a sideband channel to communicate sideband messages between the adapter and the other adapter over the physical layer. The adapter is to implement a logical PHY for the link.

Abstract: Embodiments herein describe a FEC codec for generating a check byte for a message. The FEC codec includes a port encoder having a storage unit, a Galois field multiplier, and a sum unit. The storage unit stores a first staged result, which is accumulated based on previous sets of input bytes of the message for all clock cycles from a first clock cycle to a clock cycle immediately prior to the current clock cycle. The Galois field multiplier performs a Galois field multiplication of the first staged result and a power of the alpha to generate a Galois field product. The sum unit performs a Galois field addition on an internal input based on a consolidated byte for the current clock cycle and the Galois field product to generate a second staged result for subsequent use to generate the check byte. Other embodiments may be described and/or claimed.

Abstract: Systems, methods, and computer-readable media are disclosed for an apparatus coupled to a communication bus, where the apparatus includes a queue and a controller to manage operations of the queue. The queue includes a first space to store a first information for a first traffic type, with a first flow class, and for a first virtual channel of communication between a first communicating entity and a second communicating entity. The queue further includes a second space to store a second information for a second traffic type, with a second flow class, and for a second virtual channel of communication between a third communicating entity and a fourth communicating entity. The first traffic type is different from the second traffic type, the first flow class is different from the second flow class, or the first virtual channel is different from the second virtual channel. Other embodiments may be described and/or claimed.