Patents by Inventor SWAMINATHAN T. SRINIVASAN

SWAMINATHAN T. SRINIVASAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170330750
    Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.
    Type: Application
    Filed: August 3, 2017
    Publication date: November 16, 2017
    Inventors: Swaminathan T. SRINIVASAN, Fareen Adeni KHAJA, Errol Antonio C. SANCHEZ, Patrick M. MARTIN
  • Patent number: 9799531
    Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: October 24, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Swaminathan T. Srinivasan, Fareen Adeni Khaja, Errol Antonio C. Sanchez, Patrick M. Martin
  • Publication number: 20170263466
    Abstract: Embodiments disclosed herein generally relate to methods and apparatus for processing of the bottom surface of a substrate to counteract thermal stresses thereon. Correcting strains are applied to the bottom surface of the substrate which compensate for undesirable strains and distortions on the top surface of the substrate. Specifically designed films may be formed on the back side of the substrate by any combination of deposition, implant, thermal treatment, and etching to create strains that compensate for unwanted distortions of the substrate. In some embodiments, localized strains may be introduced by locally altering the hydrogen content of a silicon nitride film or a carbon film, among other techniques. Structures may be formed by printing, lithography, or self-assembly techniques. Treatment of the layers of film is determined by the stress map desired and includes annealing, implanting, melting, or other thermal treatments.
    Type: Application
    Filed: March 10, 2017
    Publication date: September 14, 2017
    Inventors: Joseph M. RANISH, Aaron Muir HUNTER, Swaminathan T. SRINIVASAN
  • Publication number: 20170130359
    Abstract: A method and apparatus for processing a semiconductor substrate is described. The apparatus is a process chamber having an optically transparent upper dome and lower dome. Vacuum is maintained in the process chamber during processing. The upper dome is thermally controlled by flowing a thermal control fluid along the upper dome outside the processing region. Thermal lamps are positioned proximate the lower dome, and thermal sensors are disposed among the lamps. The lamps are powered in zones, and a controller adjusts power to the lamp zones based on data received from the thermal sensors.
    Type: Application
    Filed: January 26, 2017
    Publication date: May 11, 2017
    Inventors: Joseph M. RANISH, Paul BRILLHART, Jose Antonio MARIN, Satheesh KUPPURAO, Balasubramanian RAMACHANDRAN, Swaminathan T. SRINIVASAN, Mehmet Tugrul SAMIR
  • Publication number: 20170133328
    Abstract: Embodiments disclosed herein generally relate to methods and apparatus for processing of the bottom surface of a substrate to counteract thermal stresses thereon. Correcting strains are applied to the bottom surface of the substrate which compensate for undesirable strains and distortions on the top surface of the substrate. Specifically designed films may be formed on the back side of the substrate by any combination of deposition, implant, thermal treatment, and etching to create strains that compensate for unwanted distortions of the substrate. Localized strains may be introduced by locally altering the hydrogen content of a silicon nitride film or a carbon film. Structures may be formed by printing, lithography, or self-assembly techniques. Treatment of the layers of film is determined by the stress map desired and includes annealing, implanting, melting, or other thermal treatments.
    Type: Application
    Filed: October 10, 2016
    Publication date: May 11, 2017
    Inventors: Joseph M. RANISH, Aaron Muir HUNTER, Swaminathan T. SRINIVASAN
  • Patent number: 9580835
    Abstract: A method and apparatus for processing a semiconductor substrate is described. The apparatus is a process chamber having an optically transparent upper dome and lower dome. Vacuum is maintained in the process chamber during processing. The upper dome is thermally controlled by flowing a thermal control fluid along the upper dome outside the processing region. Thermal lamps are positioned proximate the lower dome, and thermal sensors are disposed among the lamps. The lamps are powered in zones, and a controller adjusts power to the lamp zones based on data received from the thermal sensors.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: February 28, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Joseph M. Ranish, Paul Brillhart, Jose Antonio Marin, Satheesh Kuppurao, Balasubramanian Ramachandran, Swaminathan T. Srinivasan, Mehmet Tugrul Samir
  • Publication number: 20170011917
    Abstract: Embodiments of the present disclosure provide methods and apparatus for forming an epitaxial layer on a substrate. The substrate is exposed to pulsed laser radiation to clean, anneal, and/or activate the surface of the substrate. The substrate is then exposed to a deposition precursor in a self-limiting deposition process. The substrate may again be exposed to pulsed laser radiation, and then exposed to a second deposition precursor in a second self-limiting deposition process. The process may be repeated as desired to form an epitaxial layer of very high quality one atomic layer at a time.
    Type: Application
    Filed: September 26, 2016
    Publication date: January 12, 2017
    Inventors: Swaminathan T. SRINIVASAN, Aaron Muir HUNTER, Matthias BAUER, Amikam SADE
  • Publication number: 20160307774
    Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.
    Type: Application
    Filed: June 28, 2016
    Publication date: October 20, 2016
    Inventors: Swaminathan T. SRINIVASAN, Fareen Adeni KHAJA, Errol Antonio C. SANCHEZ, Patrick M. MARTIN
  • Patent number: 9455143
    Abstract: Embodiments of the present disclosure provide methods and apparatus for forming an epitaxial layer on a substrate. The substrate is exposed to pulsed laser radiation to clean, anneal, and/or activate the surface of the substrate. The substrate is then exposed to a deposition precursor in a self-limiting deposition process. The substrate may again be exposed to pulsed laser radiation, and then exposed to a second deposition precursor in a second self-limiting deposition process. The process may be repeated as desired to form an epitaxial layer of very high quality one atomic layer at a time.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: September 27, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Swaminathan T. Srinivasan, Aaron Muir Hunter, Matthias Bauer, Amikam Sade
  • Patent number: 9443728
    Abstract: Implementations of the present disclosure generally relate to methods and apparatus for forming a film on a substrate. More particularly, implementations of the present disclosure relate to methods and apparatus for heteroepitaxial growth of crystalline films. In one implementation, a method of heteroepitaxial deposition of a strain relaxed buffer (SRB) layer on a substrate is provided. The method comprises epitaxially depositing a buffer layer over a dissimilar substrate, rapidly heating the buffer layer to relax the buffer layer, rapidly cooling the buffer layer and determining whether the buffer layer has achieved a desired thickness.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: September 13, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Swaminathan T. Srinivasan, Atif M. Noori, David K. Carlson
  • Patent number: 9406507
    Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: August 2, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Swaminathan T. Srinivasan, Fareen Adeni Khaja, Errol Antonio C. Sanchez, Patrick M. Martin
  • Publication number: 20160138188
    Abstract: A method and apparatus for processing a semiconductor substrate is described. The apparatus is a process chamber having an optically transparent upper dome and lower dome. Vacuum is maintained in the process chamber during processing. The upper dome is thermally controlled by flowing a thermal control fluid along the upper dome outside the processing region. Thermal lamps are positioned proximate the lower dome, and thermal sensors are disposed among the lamps. The lamps are powered in zones, and a controller adjusts power to the lamp zones based on data received from the thermal sensors.
    Type: Application
    Filed: January 4, 2016
    Publication date: May 19, 2016
    Inventors: Joseph M. RANISH, Paul BRILLHART, Jose Antonio MARIN, Satheesh KUPPURAO, Balasubramanian RAMACHANDRAN, Swaminathan T. SRINIVASAN, Mehmet Tugrul SAMIR
  • Publication number: 20160013046
    Abstract: Embodiments of the present disclosure provide methods and apparatus for forming an epitaxial layer on a substrate. The substrate is exposed to pulsed laser radiation to clean, anneal, and/or activate the surface of the substrate. The substrate is then exposed to a deposition precursor in a self-limiting deposition process. The substrate may again be exposed to pulsed laser radiation, and then exposed to a second deposition precursor in a second self-limiting deposition process. The process may be repeated as desired to form an epitaxial layer of very high quality one atomic layer at a time.
    Type: Application
    Filed: July 1, 2015
    Publication date: January 14, 2016
    Inventors: SWAMINATHAN T. SRINIVASAN, Aaron Muir Hunter, Matthias Bauer, Amikam Sade
  • Patent number: 9230837
    Abstract: A substrate processing apparatus is provided. The substrate processing apparatus includes a vacuum chamber having a dome and a floor. A substrate support is disposed inside the vacuum chamber. A plurality of thermal lamps are arranged in a lamphead and positioned proximate the floor of the vacuum chamber. A reflector is disposed proximate the dome, where the reflector and the dome together define a thermal control space. The substrate processing apparatus further includes a plurality of power supplies coupled to the thermal lamps and a controller for adjusting the power supplies to control a temperature in the vacuum chamber.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: January 5, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Joseph M. Ranish, Paul Brillhart, Jose Antonio Marin, Satheesh Kuppurao, Balasubramanian Ramachandran, Swaminathan T. Srinivasan, Mehmet Tugrul Samir
  • Publication number: 20150311292
    Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.
    Type: Application
    Filed: March 18, 2015
    Publication date: October 29, 2015
    Inventors: Swaminathan T. SRINIVASAN, Fareen Adeni KHAJA, Errol Antonio C. SANCHEZ, Patrick M. MARTIN
  • Publication number: 20150099350
    Abstract: Embodiments of the present disclosure generally relate to doping and annealing substrates. The substrates may be doped during a hot implantation process, and subsequently annealed using a nanosecond annealing process. The combination of hot implantation and nanosecond annealing reduces lattice damage of the substrates and facilitates a higher dopant concentration near the surface of the substrate to facilitate increased electrical contact with the substrate. An optional capping layer may be placed over the substrate to reduce outgassing of dopants or to control dopant implant depth.
    Type: Application
    Filed: October 1, 2014
    Publication date: April 9, 2015
    Inventors: Swaminathan T. SRINIVASAN, Fareen Adeni KHAJA
  • Publication number: 20150047566
    Abstract: Embodiments of the disclosure relate to an apparatus for processing a semiconductor substrate. The apparatus includes a process chamber having a substrate support for supporting a substrate, a lower dome and an upper dome opposing the lower dome, a plurality of gas injects disposed within a sidewall of the process chamber. The apparatus includes a gas delivery system coupled to the process chamber via the plurality of gas injects, the gas delivery system includes a gas conduit providing one or more chemical species to the plurality of gas injects via a first fluid line, a dopant source providing one or more dopants to the plurality of gas injects via a second fluid line, and a fast switching valve disposed between the second fluid line and the process chamber, wherein the fast switching valve switches flowing of the one or more dopants between the process chamber and an exhaust.
    Type: Application
    Filed: July 28, 2014
    Publication date: February 19, 2015
    Inventors: Errol Antonio C. SANCHEZ, Swaminathan T. SRINIVASAN
  • Publication number: 20150050753
    Abstract: Implementations of the present disclosure generally relate to methods and apparatus for forming a film on a substrate. More particularly, implementations of the present disclosure relate to methods and apparatus for heteroepitaxial growth of crystalline films. In one implementation, a method of heteroepitaxial deposition of a strain relaxed buffer (SRB) layer on a substrate is provided. The method comprises epitaxially depositing a buffer layer over a dissimilar substrate, rapidly heating the buffer layer to relax the buffer layer, rapidly cooling the buffer layer and determining whether the buffer layer has achieved a desired thickness.
    Type: Application
    Filed: August 15, 2014
    Publication date: February 19, 2015
    Inventors: Swaminathan T. SRINIVASAN, Atif M. NOORI, David K. CARLSON
  • Publication number: 20140273419
    Abstract: A substrate processing apparatus is provided. The substrate processing apparatus includes a vacuum chamber having a dome and a floor. A substrate support is disposed inside the vacuum chamber. A plurality of thermal lamps are arranged in a lamphead and positioned proximate the floor of the vacuum chamber. A reflector is disposed proximate the dome, where the reflector and the dome together define a thermal control space. The substrate processing apparatus further includes a plurality of power supplies coupled to the thermal lamps and a controller for adjusting the power supplies to control a temperature in the vacuum chamber.
    Type: Application
    Filed: May 30, 2014
    Publication date: September 18, 2014
    Inventors: Joseph M. RANISH, Paul BRILLHART, Jose Antonio MARIN, Satheesh KUPPURAO, Balasubramanian RAMACHANDRAN, Swaminathan T. SRINIVASAN, Mehmet Tugrul SAMIR
  • Publication number: 20140199785
    Abstract: A method and apparatus for processing a semiconductor substrate is described. The apparatus is a process chamber having an optically transparent upper dome and lower dome. Vacuum is maintained in the process chamber during processing. The upper dome is thermally controlled by flowing a thermal control fluid along the upper dome outside the processing region. Thermal lamps are positioned proximate the lower dome, and thermal sensors are disposed among the lamps. The lamps are powered in zones, and a controller adjusts power to the lamp zones based on data received from the thermal sensors.
    Type: Application
    Filed: March 12, 2013
    Publication date: July 17, 2014
    Inventors: Joseph M. RANISH, Paul BRILLHART, Jose Antonio MARIN, Satheesh KUPPURAO, Balasubramanian RAMACHANDRAN, Swaminathan T. SRINIVASAN, Mehmet Tugrul SAMIR