Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lowers-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-first-tiers or a lower of the upper-first-tiers comprises non-stoichiometric silicon nitride comprising (a) or (b), where (a): a nitrogen-to-silicon atomic ratio greater than 1.33 and less than 1.5; and (b): a nitrogen-to-silicon atomic ratio greater than or equal to 1.0 and less than 1.33. A higher of the upper-first-tiers that is above said lower upper-first-tier comprises silicon nitride not having either the (a) or the (b).

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.

Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising a vertically alternating sequence of insulative structures and additional insulative structures, at least some of the additional insulative structures comprising silicon nitride having a ratio of nitrogen atoms to silicon atoms greater than about 1.58:1.00, forming openings through the stack structure, and forming cell pillar structures within the openings, the cell pillar structures individually comprising a semiconductor channel material vertically extending through the stack structure. Related methods, microelectronic devices, memory devices, and electronic systems are also described.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lowers-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-first-tiers or a lower of the upper-first-tiers comprises non-stoichiometric silicon nitride comprising (a) or (b), where (a): a nitrogen-to-silicon atomic ratio greater than 1.33 and less than 1.5; and (b): a nitrogen-to-silicon atomic ratio greater than or equal to 1.0 and less than 1.33. A higher of the upper-first-tiers that is above said lower upper-first-tier comprises silicon nitride not having either the (a) or the (b).

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lowers-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-first-tiers or a lower of the upper-first-tiers comprises non-stoichiometric silicon nitride comprising (a) or (b), where (a): a nitrogen-to-silicon atomic ratio greater than 1.33 and less than 1.5; and (b): a nitrogen-to-silicon atomic ratio greater than or equal to 1.0 and less than 1.33. A higher of the upper-first-tiers that is above said lower upper-first-tier comprises silicon nitride not having either the (a) or the (b).

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lower-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-second-tiers or a lower of the upper-second-tiers comprises non-stoichiometric silicon dioxide that has a silicon-to-oxygen atomic ratio greater than 0.5. A higher of the upper-second-tiers that is above said lower upper-second-tier comprises silicon dioxide that has a silicon-to-oxygen atomic ratio less than or equal to 0.5. Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-second-tier or said lower upper-second-tier.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lower-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-second-tiers or a lower of the upper-second-tiers comprises non-stoichiometric silicon dioxide that has a silicon-to-oxygen atomic ratio greater than 0.5. A higher of the upper-second-tiers that is above said lower upper-second-tier comprises silicon dioxide that has a silicon-to-oxygen atomic ratio less than or equal to 0.5. Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-second-tier or said lower upper-second-tier.

Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising a vertically alternating sequence of insulative structures and additional insulative structures, at least some of the additional insulative structures comprising silicon nitride having a ratio of nitrogen atoms to silicon atoms greater than about 1.58:1.00, forming openings through the stack structure, and forming cell pillar structures within the openings, the cell pillar structures individually comprising a semiconductor channel material vertically extending through the stack structure. Related methods, microelectronic devices, memory devices, and electronic systems are also described.

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lower-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-second-tiers or a lower of the upper-second-tiers comprises non-stoichiometric silicon dioxide that has a silicon-to-oxygen atomic ratio greater than 0.5. A higher of the upper-second-tiers that is above said lower upper-second-tier comprises silicon dioxide that has a silicon-to-oxygen atomic ratio less than or equal to 0.5. Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-second-tier or said lower upper-second-tier.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lowers-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-first-tiers or a lower of the upper-first-tiers comprises non-stoichiometric silicon nitride comprising (a) or (b), where (a): a nitrogen-to-silicon atomic ratio greater than 1.33 and less than 1.5; and (b): a nitrogen-to-silicon atomic ratio greater than or equal to 1.0 and less than 1.33. A higher of the upper-first-tiers that is above said lower upper-first-tier comprises silicon nitride not having either the (a) or the (b).

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.

Abstract: A memory structure can include a memory cell and a first barrier layer having a maximum hydrogen diffusion coefficient of 1×10?17 cm2/s, said first barrier layer adjacent to the memory cell to minimize contaminant movement to or from the memory cell.

Abstract: Devices and systems having a diffusion barrier for limiting diffusion of a phase change material including an electrode, a phase change material electrically coupled to the electrode, and a carbon and TiN (C:TiN) diffusion barrier disposed between the electrode and the phase change material to limit diffusion of the phase change material are disclosed and described.

Abstract: A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.

Abstract: The disclosed technology relates to integrate circuits, including memory devices. A method of forming an integrated circuit comprises providing a surface comprising a first region and a second region, wherein the first region is formed of a different material than the second region. The method additionally comprises forming a seeding material in contact with and across the first and second regions. The method further comprises forming a metal comprising tungsten on the seeding material.

Abstract: A memory structure can include a memory cell and a first barrier layer having a maximum hydrogen diffusion coefficient of 1×10?17 cm2/s, said first barrier layer adjacent to the memory cell to minimize contaminant movement to or from the memory cell.