Patents by Inventor Swapnil Lengade

Swapnil Lengade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10950791
    Abstract: Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, and a second electrode portion is coupled to the second chalcogenide structure. An electrically conductive barrier material is disposed between the first and second electrode portions.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Swapnil A. Lengade, John M. Meldrim, Andrea Gotti
  • Patent number: 10903276
    Abstract: The disclosed technology relates to integrate circuits, including memory devices. A method of forming an integrated circuit comprises providing a surface comprising a first region and a second region, wherein the first region is formed of a different material than the second region. The method additionally comprises forming a seeding material in contact with and across the first and second regions. The method further comprises forming a metal comprising tungsten on the seeding material.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tsz Wah Chan, Yongjun J. Hu, Swapnil Lengade
  • Publication number: 20200321523
    Abstract: Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A component of a memory cell, such as a selector device, storage device, or self-selecting memory device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. The chalcogenide material, for instance, may have a composition of selenium, germanium, and at least one of boron, aluminum, gallium, indium, or thallium. The chalcogenide material may in some cases also include arsenic, but may in some cases lack arsenic.
    Type: Application
    Filed: June 18, 2020
    Publication date: October 8, 2020
    Inventors: Enrico Varesi, Paolo Fantini, Lorenzo Fratin, Swapnil A. Lengade
  • Publication number: 20200303642
    Abstract: A memory structure can include a memory cell and a first barrier layer having a maximum hydrogen diffusion coefficient of 1×10?17 cm2/s, said first barrier layer adjacent to the memory cell to minimize contaminant movement to or from the memory cell.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Inventors: Karthik Sarpatwari, Dale Collins, Anna Maria Conti, Fred Daniel Gealy, III, Andrea Gotti, Swapnil Lengade, Stephen Russell
  • Patent number: 10727405
    Abstract: Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A component of a memory cell, such as a selector device, storage device, or self-selecting memory device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. The chalcogenide material, for instance, may have a composition of selenium, germanium, and at least one of boron, aluminum, gallium, indium, or thallium. The chalcogenide material may in some cases also include arsenic, but may in some cases lack arsenic.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Enrico Varesi, Paolo Fantini, Lorenzo Fratin, Swapnil A. Lengade
  • Patent number: 10720574
    Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: July 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Tsz W. Chan, Yongjun Jeff Hu, Swapnil Lengade, Shu Qin, Everett Allen McTeer
  • Publication number: 20200203606
    Abstract: A memory structure can include a memory cell and a first barrier layer having a maximum hydrogen diffusion coefficient of 1×10?17 cm2/s, said first barrier layer adjacent to the memory cell to minimize contaminant movement to or from the memory cell.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Applicant: Intel Corporation
    Inventors: Karthik Sarpatwari, Dale Collins, Anna Maria Conti, Fred Daniel Gealy, III, Andrea Gotti, Swapnil Lengade, Stephen Russell
  • Patent number: 10680175
    Abstract: A memory structure can include a memory cell and a first barrier layer having a maximum hydrogen diffusion coefficient of 1×10?17 cm2/s, said first barrier layer adjacent to the memory cell to minimize contaminant movement to or from the memory cell.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: Karthik Sarpatwari, Dale Collins, Anna Maria Conti, Fred Daniel Gealy, III, Andrea Gotti, Swapnil Lengade, Stephen Russell
  • Patent number: 10651381
    Abstract: Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, a second electrode portion is coupled to the second chalcogenide structure, and a third electrode portion is between the first and second electrode portions. A first portion of an electrically conductive barrier material is disposed between the first and third electrode portions. A second portion of the electrically conductive barrier material is disposed between the second and third electrode portions.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: May 12, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Swapnil A. Lengade, John M. Meldrim, Andrea Gotti
  • Publication number: 20200091244
    Abstract: The disclosed technology relates to integrate circuits, including memory devices. A method of forming an integrated circuit comprises providing a surface comprising a first region and a second region, wherein the first region is formed of a different material than the second region. The method additionally comprises forming a seeding material in contact with and across the first and second regions. The method further comprises forming a metal comprising tungsten on the seeding material.
    Type: Application
    Filed: November 15, 2019
    Publication date: March 19, 2020
    Inventors: Tsz Wah Chan, Yongjun J. Hu, Swapnil Lengade
  • Patent number: 10546895
    Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: January 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yongjun Jeff Hu, Tsz W. Chan, Swapnil Lengade, Everett Allen McTeer, Shu Qin
  • Patent number: 10510805
    Abstract: The disclosed technology relates to integrate circuits, including memory devices. A method of forming an integrated circuit comprises providing a surface comprising a first region and a second region, wherein the first region is formed of a different material than the second region. The method additionally comprises forming a seeding material in contact with and across the first and second regions. The method further comprises forming a metal comprising tungsten on the seeding material.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: December 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Tsz Wah Chan, Yongjun J. Hu, Swapnil Lengade
  • Publication number: 20190355902
    Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.
    Type: Application
    Filed: February 4, 2019
    Publication date: November 21, 2019
    Inventors: Tsz W. Chan, Yongjun Jeff Hu, Swapnil Lengade, Shu Qin, Everett Allen McTeer
  • Patent number: 10439000
    Abstract: Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A memory device, such as a selector device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. A selector device, for instance, may have a composition of selenium, arsenic, and at least one of boron, aluminum, gallium, indium, or thallium. The selector device may also be composed of germanium or silicon, or both. The relative amount of boron, aluminum, gallium, indium, or thallium may affect a threshold voltage of a memory component, and the relative amount may be selected accordingly. A memory component may, for instance have a composition that includes selenium, arsenic, and some combination of germanium, silicon, and at least one of boron, aluminum, gallium, indium, or thallium.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Fantini, F. Daniel Gealy, Enrico Varesi, Swapnil A. Lengade
  • Patent number: 10347831
    Abstract: Doping a storage element, a selector element, or both, of a memory cell with a dopant including one or more of aluminum (Al), zirconium (Zr), hafnium (Hf), and silicon (Si), can minimize volume or density changes in a phase change memory as well as minimize electromigration, in accordance with embodiments. In one embodiment, a memory cell includes a first electrode and a second electrode, and a storage element comprising a layer of doped phase change material between the first and second electrodes, wherein the doped phase change material includes one or more of aluminum, zirconium, hafnium, and silicon. The storage element, a selector element, or both can be doped using techniques such as cosputtering or deposition of alternating layers of a dopant layer and a storage (or selector) material.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Daniel Gealy, Andrea Gotti, Dale W. Collins, Swapnil A. Lengade
  • Publication number: 20190140023
    Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner.
    Type: Application
    Filed: January 7, 2019
    Publication date: May 9, 2019
    Inventors: Yongjun Jeff Hu, Tsz W. Chan, Swapnil Lengade, Everett Allen McTeer, Shu Qin
  • Publication number: 20190115532
    Abstract: Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A component of a memory cell, such as a selector device, storage device, or self-selecting memory device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. The chalcogenide material, for instance, may have a composition of selenium, germanium, and at least one of boron, aluminum, gallium, indium, or thallium. The chalcogenide material may in some cases also include arsenic, but may in some cases lack arsenic.
    Type: Application
    Filed: December 20, 2018
    Publication date: April 18, 2019
    Inventors: Enrico Varesi, Paolo Fantini, Lorenzo Fratin, Swapnil A. Lengade
  • Patent number: 10256406
    Abstract: A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: April 9, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Dale W. Collins, Andrea Gotti, F. Daniel Gealy, Tuman E. Allen, Swapnil Lengade
  • Publication number: 20190097133
    Abstract: A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.
    Type: Application
    Filed: November 28, 2018
    Publication date: March 28, 2019
    Inventors: Dale W. Collins, Andrea Gotti, F. Daniel Gealy, Tuman E. Allen, Swapnil Lengade
  • Publication number: 20190088867
    Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall.
    Type: Application
    Filed: January 29, 2018
    Publication date: March 21, 2019
    Inventors: Tsz W. Chan, Yongjun Jeff Hu, Swapnil Lengade, Shu Qin, Everett Allen McTeer