Abstract: Various devices, methods and systems are provided for aging-sensitive chip authentication. In one example, among others, a chip includes a reference Schmitt trigger ring oscillator (STRO) configured to enter a sleep mode during operation of the chip; a stressed STRO; a VDD charge pump configured to boost a positive voltage supplied to the stressed STRO during operation of the chip; and/or a GND charge pump configured to under-drive a ground voltage supplied to the stressed STRO during operation of the chip. In another example, a method includes detecting activation of a chip including a reference STRO and a stressed STRO and, in response to the activation of the chip, initiating sleep mode operation of the reference STRO. In response to the activation of the chip, a VDD voltage supplied to the stressed STRO can be boosted and/or a GND voltage supplied to the stressed STRO can be under-driven.

Abstract: Various devices, methods and systems are provided for aging-sensitive chip authentication. In one example, among others, a chip includes a reference Schmitt trigger ring oscillator (STRO) configured to enter a sleep mode during operation of the chip; a stressed STRO; a VDD charge pump configured to boost a positive voltage supplied to the stressed STRO during operation of the chip; and/or a GND charge pump configured to under-drive a ground voltage supplied to the stressed STRO during operation of the chip. In another example, a method includes detecting activation of a chip including a reference STRO and a stressed STRO and, in response to the activation of the chip, initiating sleep mode operation of the reference STRO. In response to the activation of the chip, a VDD voltage supplied to the stressed STRO can be boosted and/or a GND voltage supplied to the stressed STRO can be under-driven.

Abstract: Various devices, methods and systems are provided for aging-sensitive chip authentication. In one example, among others, a chip includes a reference Schmitt trigger ring oscillator (STRO) configured to enter a sleep mode during operation of the chip; a stressed STRO; a VDD charge pump configured to boost a positive voltage supplied to the stressed STRO during operation of the chip; and/or a GND charge pump configured to under-drive a ground voltage supplied to the stressed STRO during operation of the chip. In another example, a method includes detecting activation of a chip including a reference STRO and a stressed STRO and, in response to the activation of the chip, initiating sleep mode operation of the reference STRO. In response to the activation of the chip, a VDD voltage supplied to the stressed STRO can be boosted and/or a GND voltage supplied to the stressed STRO can be under-driven.

Abstract: Disclosed are various embodiments providing circuitry that includes camouflaged gates that each have multiple switches arranged in a predefined format. A switch at a specific position in one camouflaged gate can have a different threshold voltage than a switch at the specific position in another camouflaged gate. The logical function performed by the camouflaged gate can be based on which of the switches have a low threshold voltage and which of the switches have a high threshold voltage.

Abstract: Disclosed are various embodiments providing circuitry that includes camouflaged gates that each have multiple switches arranged in a predefined format. A switch at a specific position in one camouflaged gate can have a different threshold voltage than a switch at the specific position in another camouflaged gate. The logical function performed by the camouflaged gate can be based on which of the switches have a low threshold voltage and which of the switches have a high threshold voltage.

Abstract: Various devices, methods and systems are provided for aging-sensitive chip authentication. In one example, among others, a chip includes a reference Schmitt trigger ring oscillator (STRO) configured to enter a sleep mode during operation of the chip; a stressed STRO; a VDD charge pump configured to boost a positive voltage supplied to the stressed STRO during operation of the chip; and a GND charge pump configured to under-drive a ground voltage supplied to the stressed STRO during operation of the chip. In another example, a method includes detecting activation of a chip including a reference STRO and a stressed STRO and, in response to the activation of the chip, initiating sleep mode operation of the reference STRO. In response to the activation of the chip, a VDD voltage supplied to the stressed STRO can be boosted and/or a GND voltage supplied to the stressed STRO can be under-driven.

Abstract: Aspects of wide operating range level shifter designs are described. One embodiment includes a level shifter configured to receive an input signal in a first voltage domain and generate an output signal in a second voltage domain, a pulse generator configured to generate a pulse in response to sensing a rise transition on the input signal, and a droop circuit configured to decouple at least a portion of the level shifter from the second voltage domain in response to the pulse. According to one aspect of the embodiments, the pulse can be provided to the droop circuit to decouple at least a portion of the level shifter from the second voltage domain and reduce contention between transistors in the level shifter. Using the concepts described herein, the worst case rise time delay for level shifters can be significantly reduced.

Abstract: A system and method for providing a physically unclonable function (PFU) is described. In operation, the method includes applying a domain wall shift pulse challenge to a plurality of nanowires of a domain wall memory (DWM) array, wherein the nanowires of the domain wall memory (DWM) array have process induced variations, resulting in pinning potentials which affect the velocity of the domain walls along the length of the nanowires. Following the application of the domain wall shift pulse, the response to the challenge is determined by measuring the response of the plurality of nanowires of the domain wall memory to the applied domain wall shift pulse challenge to provide a physically unclonable function (PUF) for the integrated circuit.

Abstract: Slope detection systems and methods are provided that monitor magnetic tunnel junction (MTJ) resistance switching. A low-overhead, sample-and-hold circuit can be used. Slope detection techniques can reduce or eliminate bit-to-bit process variation, thereby reducing or eliminating variation in oxide thickness. In addition, the need for data and reference current can be obviated compared to related art techniques, thereby increasing sensing robustness.

Abstract: Embodiments of the subject invention provide a three transistor, two domain-wall-based magnetic tunnel junction CAM cell (3T-2DW-MTJ CAM). A four transistor, two magnetic tunnel junction ternary CAM cell (4T-2MTJ TCAM) is also provided. An array of the provided CAM cells forms words of various lengths, such as 4-bit, 8-bit, and 16-bit words. Longer CAM words can be formed by an array having hierarchical structures of CAM cells having smaller word sizes, such as 4-bit words or 8-bit words.

Abstract: Aspects of wide operating range level shifter designs are described. One embodiment includes a level shifter configured to receive an input signal in a first voltage domain and generate an output signal in a second voltage domain, a pulse generator configured to generate a pulse in response to sensing a rise transition on the input signal, and a droop circuit configured to decouple at least a portion of the level shifter from the second voltage domain in response to the pulse. According to one aspect of the embodiments, the pulse can be provided to the droop circuit to decouple at least a portion of the level shifter from the second voltage domain and reduce contention between transistors in the level shifter. Using the concepts described herein, the worst case rise time delay for level shifters can be significantly reduced.

Abstract: Non-volatile flip-flops (NVFFs) based circuitries and schemes that incorporate magnetic tunnel junctions (MTJs) are provided to ensure fast data storage and restoration from an intentional or unintentional power outage. The NVFFs based circuitries and schemes also include enhanced scan mode testing capability by exploiting the nonvolatile latch to function as hold latch for delay testing. The NVFFs based circuitries and schemes eliminate additional write drivers, and may operate at an operation frequency of, for example, up to 2 GHz at a supply voltage of 1.1 V and with 0.55 pJ of energy consumption. A near uniform write latency can be achieved through transistor sizing, given write asymmetry of MTJs. NVFFs based circuitries and schemes incorporating data-dependent power gating circuitries can be used to mitigate high static currents generated during retention and back-to-back writing of identical input data.

Abstract: Aspects of wide operating range level shifter designs are described. One embodiment includes a level shifter configured to receive an input signal in a first voltage domain and generate an output signal in a second voltage domain, a pulse generator configured to generate a pulse in response to sensing a rise transition on the input signal, and a droop circuit configured to decouple at least a portion of the level shifter from the second voltage domain in response to the pulse. According to one aspect of the embodiments, the pulse can be provided to the droop circuit to decouple at least a portion of the level shifter from the second voltage domain and reduce contention between transistors in the level shifter. Using the concepts described herein, the worst case rise time delay for level shifters can be significantly reduced.

Abstract: A system and method for providing a physically unclonable function (PFU) is described. In operation, the method includes applying a domain wall shift pulse challenge to a plurality of nanowires of a domain wall memory (DWM) array, wherein the nanowires of the domain wall memory (DWM) array have process induced variations, resulting in pinning potentials which affect the velocity of the domain walls along the length of the nanowires. Following the application of the domain wall shift pulse, the response to the challenge is determined by measuring the response of the plurality of nanowires of the domain wall memory to the applied domain wall shift pulse challenge to provide a physically unclonable function (PUF) for the integrated circuit.

Abstract: Embodiments of the subject invention provide a three transistor, two domain-wall-based magnetic tunnel junction CAM cell (3T-2DW-MTJ CAM). A four transistor, two magnetic tunnel junction ternary CAM cell (4T-2MTJ TCAM) is also provided. An array of the provided CAM cells forms words of various lengths, such as 4-bit, 8-bit, and 16-bit words. Longer CAM words can be formed by an array having hierarchical structures of CAM cells having smaller word sizes, such as 4-bit words or 8-bit words.

Abstract: A Magnetic Tunnel Junction (MJT) Ternary Content Addressable Memory (TCAM) employing six transistors and exhibiting reduced standby leakage and improved area-efficiency. In the proposed TCAM, data can be written to the MJT devices by conventional current induced magnetization techniques and by controlling the source line, thereby eliminating the need for external writing circuitry.

Abstract: Slope detection systems and methods are provided that monitor magnetic tunnel junction (MTJ) resistance switching. A low-overhead, sample-and-hold circuit can be used. Slope detection techniques can reduce or eliminate bit-to-bit process variation, thereby reducing or eliminating variation in oxide thickness. In addition, the need for data and reference current can be obviated compared to related art techniques, thereby increasing sensing robustness.

Abstract: Non-volatile flip-flops (NVFFs) based circuitries and schemes that incorporate magnetic tunnel junctions (MTJs) are provided to ensure fast data storage and restoration from an intentional or unintentional power outage. The NVFFs based circuitries and schemes also include enhanced scan mode testing capability by exploiting the nonvolatile latch to function as hold latch for delay testing. The NVFFs based circuitries and schemes eliminate additional write drivers, and may operate at an operation frequency of, for example, up to 2 GHz at a supply voltage of 1.1 V and with 0.55 pJ of energy consumption. A near uniform write latency can be achieved through transistor sizing, given write asymmetry of MTJs. NVFFs based circuitries and schemes incorporating data-dependent power gating circuitries can be used to mitigate high static currents generated during retention and back-to-back writing of identical input data.

Abstract: Disclosed is a pulsed sense amplifier approach for resolving data on a bit line. A chip is provided which comprises a sense amplifier coupled to first and second DRAM bitlines; and a circuit having a trigger node coupled to the sense amp to transition it from a first state to a second state to trigger the sense amp, the circuit having an element to impede the transition once it is initiated. A chip is described which comprises: a DRAM array having a plurality of bitlines; sense amplifiers to resolve data on the bit lines, and a circuit to slow down resolution of the data by the sense amps after they have been triggered to resolve the data.

Abstract: Disclosed is a pulsed sense amplifier approach for resolving data on a bit line.