Patents by Inventor Swaroop Ghosh

Swaroop Ghosh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Nor logic word line selection
    Patent number: 8547777
    Abstract: A NOR architecture for selecting a word line driver in a DRAM is disclosed. Complements of separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: October 1, 2013
    Assignee: Intel Corporation
    Inventors: Swaroop Ghosh, Dinesh Somasekhar, Balaji Srinivasan, Fatih Hamzaoglu
  • NAND logic word line selection
    Patent number: 8456946
    Abstract: A NAND architecture for selecting a word line driver in a DRAM is disclosed. Separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: June 4, 2013
    Assignee: Intel Corporation
    Inventors: Swaroop Ghosh, Dinesh Somasekhar, Balaji Srinivasan, Fatih Hamzaoglu
  • Hierarchical DRAM sensing
    Patent number: 8406073
    Abstract: A hierarchical DRAM sensing apparatus and method which employs local bit line pairs and global bit lines. A word line selects the cells in a cluster of sense amplifiers, each of the amplifiers being associated with a pair of bit lines. One of the local bit lines is selected for coupling to global bit lines and a global sense amplifier. Clusters are located in a plurality of subarrays forming a bank with the global bit lines extending from each of the banks to the global sense amplifier.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: March 26, 2013
    Assignee: Intel Corporation
    Inventors: Dinesh Somasekhar, Gunjan Pandya, Kevin Zhang, Fatih Hamzaoglu, Balaji Srinivasan, Swaroop Ghosh, Meterelliyoz Mesut
  • NAND logic word line selection
    Publication number: 20120163114
    Abstract: A NAND architecture for selecting a word line driver in a DRAM is disclosed. Separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Inventors: Swaroop Ghosh, Dinesh Somasekhar, Balaji Srinivasan, Fatih Hamzaoglu
  • Nor logic word line selection
    Publication number: 20120163115
    Abstract: A NOR architecture for selecting a word line driver in a DRAM is disclosed. Complements of separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Inventors: Swaroop Ghosh, Dinesh Somasekhar, Balaji Srinivasan, Fatih Hamzaoglu