Abstract: A method and system are directed to generating on-chip bitstreams on reconfigurable hardware. The system comprises a built-in bitstream initialization (BIBI) module configured to generate one or more bitstreams on a semiconductor device. The BIBI module comprising a sequence generator configured to generate a sequence of values for each of the one or more bitstreams, a masking module configured to convert the sequence of values to a given precision of bits, an encryption module configured to apply an encryption scheme to the sequence of values, and an error correction module configured to apply error correction on the sequence of values, wherein the one or more bitstreams are transmitted to a routing network configured to map the one or more bitstreams to input positions of one or more compute blocks.

Abstract: The present disclosure describes various embodiments of systems, apparatuses, and methods for drone-based administration of remotely located devices. One such method comprises deploying an unmanned aerial vehicle from a base station, wherein the base station assigns a maintenance order to the unmanned aerial vehicle for servicing of a remote device, traveling, by the unmanned aerial vehicle, to the location of the remote device, authenticating, by the unmanned aerial vehicle, a valid identification of the remote device; upon the remote device being authenticated by the unmanned aerial vehicle, servicing the remote device by at least charging a power supply of the remote device and transferring contents of a device log to the unmanned aerial vehicle; and after completing the servicing of the remote device; returning to the base station and transferring contents of the device log to the base station.

Abstract: The present disclosure describes systems, apparatuses, and methods for obfuscation-based intellectual property (IP) watermark labeling. One such method comprises identifying, by one or more computing processors, a specific net within an integrated circuit design that is likely to be used in a malicious attack; and adding additional nets to the integrated circuit design that add additional logic states to a finite state machine present in the integrated circuit design. The additional logic states comprise watermarking states for performing authentication of the integrated circuit design, in which a watermark digest can be captured upon application of secret key inputs to the additional nets. Other methods, systems, and apparatuses are also presented.

Abstract: Various embodiments of the present disclosure provide a scan-based architecture for register-transfer-level (RTL) or gate-level designs that improves the security of scan chain-based design-for-testability (DFT) structures. In various embodiments, the scan-based architecture includes invisible scan chains that are hidden in such a way that an attacker cannot easily identify or locate the invisible scan chains for exploitation and revealing internal secure information of the design. The invisible scan chains are dynamically configurable into a scan chain with select flip-flops, such that scan paths of the invisible scan chains may be different between different designs, chips, or testing operations. Various embodiments further employ key-based obfuscation by combining a scan control finite state machine with existing state machines within a design, which improves design security against unauthorized use and increases confidentiality.

Abstract: A computing entity comprising an intelligent digital memory system and one or more processors communicatively coupled to the intelligent digital memory system is provided. The one or more processors configured to receive one or more storage parameters, determine a store procedure cue neuron search location from candidate ones of a plurality of cue neurons associated with a neural memory network (NoK), insert the input data as a data neuron into the NoK based on the store procedure cue neuron search location, temporally link the data neuron with a location of last insertion, and modify the NoK in a manner of accessibility based on a pattern of a search for the store procedure cue neuron search location.

Abstract: A system for secure testing and provisioning of an integrated circuit (IC) includes, in part, a secure reconfigurable key provisioning architecture (SLEEVE) module disposed in the IC, and a secure asset provisioning hardware entity (SAPHE) module. The IC may include, in part, a modified IEEE 1500 wrapper to control its operation modes. The SLEEVE module may include, in part, an encoding/decoding module and an unlocking module. The encoding/decoding module may include, in part, a decode key stream cipher module, an encode key stream cipher module, Seed Key programmable linear-feedback shift registers (LFSRs), Initialization Vector (IV) LFSRs, and configuration registers. The encoding/decoding module may be configured to generate key bits for decoding and encoding inputs and outputs of the IC. The unlocking module may include, in part, a pattern matching block and a counter. The unlocking module may be configured to enable write access to the configuration registers.

Abstract: Apparatus, systems, and methods described herein relate generally to autonomous mobile units carrying a modular configurable battery system that may attach and power mobile units in transportation systems. A method can include determining charge levels, current positions, and transport speeds for an electric vehicle (EV), identifying one or more EVs in need of charging, and mobilizing a Mobile Charging Station (MoCS) to deliver one or more external batteries. A processor, with a memory including computer program code, can be configured to receive current charge level data for mobile battery-powered entities, identify one or more EVs to be charged and the proximity of both MoCS and physical battery stations, and send charging instructions to the EVs. A routing and charge transaction scheduling algorithm can be used to optimize the route of one or more battery-powered entities and to schedule charge transactions between the EV and MoCS and/or the battery station.

Abstract: A method for fabricating nano-electro-mechanical tags for identification and authentication includes, in part, forming a protective layer above a substrate, forming a first conductive layer above the protective layer serving as a first electrode, forming a piezoelectric layer above the first conductive layer, forming a second conductive layer above the piezoelectric layer, patterning the second conductive layer to form a second electrode, patterning the piezoelectric layer to expose one or more portions of the first conductive layer, and forming one or more trenches that extends into a plurality layers formed above. In addition, a sacrificial layer can be formed above portions of the substrate, and the sacrificial layer can be removed by etching to release the nano-electro-mechanical tags from the substrate.

Abstract: An integrated circuit includes, in part, a key management unit configured to generate a seeding key during a start-up phase, an encryption module configured to encrypt data using the seeding key and deliver the encrypted data to a second integrated circuit, and an encoder configured to encode the seeding key and deliver the encoded seeding key to the second IC. The second integrated circuit includes, in part, a decoder configured to decode the seeding key. Each of the integrated circuits further includes, in part, a linear-feedback shift register that receives the same clock signals and loads the seeding key.

Abstract: Various embodiments of the present disclosure provide functional verification flow of obfuscated designs for circuits. In one example, an embodiment provides for applying an input sequence to an obfuscated design for an integrated circuit that is formatted in a hardware description language, applying the input sequence to an original design for the integrated circuit that is formatted in the hardware description language, and comparing respective outputs provided by the obfuscated design and the original design to determine functional correctness of the obfuscated design.

Abstract: Various embodiments of the present disclosure provide a multi-layered framework for security of integrated circuits. In one example, an embodiment provides for removing one or more routing tables in a Register Transfer Level (RTL) source code that models a design for an SoC via a hardware description language, comprising replacing the one or more routing tables in the RTL source code with respective programmable memory, transforming a state space of one or more embedded state machines in the RTL source code, transforming one or more portions of combinational logic in the RTL source code, and/or removing one or more portions of security-critical logic in the RTL source code, comprising replacing the one or more portions of security-critical logic in the RTL source code with respective lookup tables.

Abstract: A method of obfuscating a circuit design includes, in part, receiving a netlist of the circuit design, splitting the circuit design into a multitude of partitions, transforming each partitions so as to obfuscate each partition, and stitching the multitude of transformed partitions to form the obfuscated circuit. The netlist may be a register transfer level netlist. The number and the size of partitions may vary. The partitions may be distributed throughout the entirety of the design. The method may further include generating a randomized circuit associated with at least a subset of the partitions, and merging each partition with the partition's associated randomized circuit. The method may further include quantifying the amount of transformation associated with each partition. The method may further include adding a first key to at least one of the obfuscated partitions, and adding a second key to the partition's associated randomized circuit.

Abstract: Various embodiments of the present disclosure address technical challenges related to the battery-related constraints of battery electric vehicles (BEVs). Various embodiments described herein provide an innovative framework for replenishing BEV batteries on-the-go with the help of unmanned aerial vehicles (UAVs) and mobile charging stations (MoCS). That is, various embodiments include a mobile multi-modality recharging framework including vehicles and apparatuses configured to provide and/or receive mobile multi-modality recharging, methods for performing and/or configuring mobile multi-modality recharging, computer program products for performing operations for mobile multi-modality recharging, and/or the like. Further, various embodiments described herein provide battery replacement systems and battery storage systems that may be implemented by a BEV or a vehicle receiving mobile multi-modality recharging.

Abstract: The present disclosure provides systems and methods for timed unlocking and locking of hardware intellectual properties obfuscation. One such method includes determining whether received key inputs match a functional key sequence of an integrated circuit or a test key sequence of the integrated circuit; permanently enabling operation of the integrated circuit responsive to the received key inputs being determined to be a functional key sequence for permanently enabling operation of the integrated circuit; temporarily enabling operation of the integrated circuit responsive to the received key inputs being determined to be the test key sequence for temporarily enabling operation of the integrated circuit to perform testing of the functionality and disable thereafter; and locking sequential logic and combinational logic of the integrated circuit if the received key inputs are determined to not be either the functional key sequence or the test key sequence. Other systems and methods are also provided.

Abstract: Various embodiments of the present disclosure provide a scan-based architecture for register-transfer-level (RTL) or gate-level designs that improves the security of scan chain-based design-for-testability (DFT) structures. In various embodiments, the scan-based architecture includes invisible scan chains that are hidden in such a way that an attacker cannot easily identify or locate the invisible scan chains for exploitation and revealing internal secure information of the design. The invisible scan chains are dynamically configurable into a scan chain with select flip-flops, such that scan paths of the invisible scan chains may be different between different designs, chips, or testing operations. Various embodiments further employ key-based obfuscation by combining a scan control finite state machine with existing state machines within a design, which improves design security against unauthorized use and increases confidentiality.

Abstract: Methods and systems are directed to creating a physical unclonable function (PUF) on a Field Programmable Gate Array (FPGA) and generating a unique signature for a device. The method includes, in part, designing a PUF by taking advantages of programmable logic elements on the FPGA, and extracting uninitialized values associated with one or more storage elements comprised in the PUF when the FPGA is powered up. The extracted uninitialized values can be combined to generate the unique signature for the device. The one or more storage elements can be bi-stable memory cells that are mapped to look up tables (LUTs) on the FPGA. The coordinates of these LUTs can be determined based on hamming distance analysis. Alternatively, the one or more storage elements can be memory cells associated with boundary scan cells of a boundary scan chain.

Abstract: The present disclosure describes exemplary methods and systems of protecting an integrated circuit. One exemplary method comprises receiving a plurality of key inputs for enabling operation of the integrated circuit; determining whether the received key inputs are correct key inputs for enabling operation of the integrated circuit; and if the received key inputs are determined to be incorrect key inputs, locking sequential logic and combinational logic of the integrated circuit until correct key inputs are received.

Abstract: The present disclosure relates generally to using detected bladder events for the diagnosis of urinary incontinence or the treatment of lower urinary tract dysfunction. A system includes a sensing device comprising a pressure sensor to directly detect a pressure within a bladder. The sensing device is adapted to be located within the bladder. The system also includes a signal processing device to: receive a signal indicating the detected pressure within the bladder; detect a bladder event based the detected pressure within the signal; and characterize the bladder event as a bladder contraction event or a non-contraction event. The characterization of the bladder event can be used in the diagnosis of urinary incontinence or the treatment of lower urinary tract dysfunction.

Abstract: Embodiments provide for a learning-rooted IoT platform. In example embodiments, a plug-and-play base pad apparatus includes one or more ports, each configured for hosting a pluggable component. The plug-and-play base pad apparatus further includes one or more of an administration chip or a microcontroller configured to control the apparatus and the one or more ports. The plug-and-play base pad apparatus further includes a battery configured to power the apparatus. The plug-and-play base pad apparatus further includes a power management unit configured to monitor the battery and interface with charging mechanisms.

Abstract: An exemplary integrated nuclear quadrupole resonance-based detection system comprises a front-end device having a hand-held form factor, wherein the front-end device is configured to scan a sample in or near a sample coil using inbuild electronics and acquire a nuclear quadrupole resonance measurement. The system further includes a swappable sample coil that is attached to an opening at a face of the front-end device and is tuned to a resonant frequency of the sample; and a swappable impedance matching network that is attached to the opening at the face of the front-end device and is configured to tune the resonant frequency of the sample coil. The inbuild electronics comprises a wireless transfer module that is configured to communicate the acquired nuclear quadrupole resonance measurement with a back-end device of the integrated nuclear quadrupole resonance-based detection system. Other systems and methods are also provided.