Abstract: A reconfigurable JTAG includes, in part, a core logic, a boundary scan chain cell, one or more reconfigurable blocks (RBs), and a reconfigurable block (RB) programming module. The RBs may include, in part, one or more reconfigurable boundary scan chain blocks (RBB) adapted to couple the boundary scan chain cell to the core logic and to input/output (I/O) ports of the reconfigurable JTAG. The RBs may also include, in part, one or more additional reconfigurable logic (ARL) blocks to provide enhanced logic for locking operations. The RB programmable module may communicate with a memory storing data for configuring the RBBs and ARLs. The RB programming module may configure the RBBs and ARLs based at least in part on the data stored in the memory to disable access to the I/O ports of the JTAG. The RB programming module may configure the RBBs to encrypt the I/O ports in accordance with a cipher algorithm.

Abstract: In general, embodiments of the present disclosure provide methods, apparatus, systems, computer program products, computing devices, computing entities, and/or the like for altering a design of a hardware intellectual property (IP). In accordance with various embodiments, a representation of the design of the hardware IP is converted to generate a control and data flow graph (CDFG) for the design. An entropy analysis of the CDFG is conducted to identify one or more control paths and/or data paths for removal. Responsive to identifying control path(s) for removal, control logic for the control path(s) is removed from the design and replaced with first reconfigurable logic. Responsive to identifying data path(s) for removal, datapath logic for the data path(s) is removed from the design and replaced with second reconfigurable logic. Logic synthesis is then performed on the design, along with verification to check functional correctness of the design of the hardware.

Abstract: Embodiments of the present disclosure are directed to a portable podiatric activity tracking system for monitoring the neuromuscular gait, stance, and/or performance related to the feet of an end user. Embodiments are configured to receive, by a podiatric data central (PODAC) module, podiatry data associated with a respective foot of the end user. The podiatry data is generated at least in part by podiatry-related sensors associated with respective movable podiatry trackers (MOPTs). Embodiments can also generate, based at least in part on the podiatry data, summary data related to foot activity related to the end user. Embodiments can transmit the summary data to an end device associated with the end user. A mobile software application associated with the end device can generate active feedback based at least in part on the summary data, where the active feedback is configured to encourage or discourage the foot activity related to the end user.

Abstract: Various embodiments of the present disclosure provide electromagnetic based secure contact-less integrity verification for an integrated circuit. In one example, an embodiment provides for mapping a signal to a pseudo-random number generator (PRNG) seed value, generating a PRNG output digital signal based on the PRNG seed value, encrypting the PRNG output digital signal based on a cipher function and a key, and generating an electromagnetic signal associated with the PRNG output digital signal to facilitate non-contact sensing of the electromagnetic signal by a probing system.

Abstract: A joint compression and encryption system is configured to retrieve, from a local memory or image capture device, an image file including a first plurality of segments. The system is further configured to identify, for one or more segment of the first plurality of segments, a matching segment in a local segmentation repository. The system is further configured to compress remaining segments of the first plurality of segments for which no matching segment was identified into a compressed remaining segment set. The system is further configured to transmit, via an unsecure communication channel and to a second computing entity, the identifications of the matching segments, and the compressed remaining segment set. The system is further configured to, prior to retrieving the image file, perform a handshake or calibration process. The system is further configured to encrypt the matching segments using a key into an encrypted segment set and transmit the key to the second computing entity.

Abstract: Apparatus, systems, and methods described herein relate generally to on-the-go entity-to-entity charging for multi-level battery-powered entities in transportation systems. A method can include determining charge levels, current positions, battery configuration, and transport speeds for an electric vehicle (EV), identifying one or more EVs in need of charging, and mobilizing a nearby EV for on-the-go peer-to-peer charging. A processor, with a memory including computer program code, can be configured to receive current charge level data for mobile battery-powered entities, identify one or more EVs to be charged and one or more other EVs that have excess charge to transfer, and send charging instructions to the EVs. A routing and charge transaction scheduling algorithm can be used to optimize the route of one or more battery-powered entities and to schedule charge transactions between EVs and/or a charging entity. A heuristic battery architecture compiler can be used to optimize battery architecture.

Abstract: Methods and system are provided for designing a programmable circuitry. The method may generate a cell library with custom multi-input and multi-output configurable logic cells and introduce such in a netlist design. The methods may increase the configuration and diversity of cells to increase the security of the underlying design. The methods may to randomize the interconnects by changing a set of cells used. The methods may integrate any of the steps with electronic design automation (EDA) synthesis tools.

Abstract: A three-dimensional integrated circuit is provided. In various embodiments, the three-dimensional integrated circuit includes a first electronic module disposed on a substrate of the three-dimensional integrated circuit and a first battery disposed on the first electronic module and electronically coupled to the first electronic module. The first battery may be configured to provide power to the first electronic module. The three-dimensional integrated circuit includes a second electronic module disposed on the first battery, and a second battery disposed on the second electronic module and electronically coupled to the second electronic module. The second battery may be configured to provide power to the second electronic module.

Abstract: In general, embodiments of the present disclosure provide methods, apparatus, systems, computer program products, computing devices, and computing entities for modifying a design of a hardware IP. According to one embodiment, a method is provided, the method including generating a control and data flow graph (CDFG) representation for portions of the design. The method further includes partitioning the CDFG representation into a set of partitioned sub-graphs. The method further includes, for each partitioned sub-graph, generating a merged sub-graph to form a set of merged sub-graphs. Generating the merged sub-graph for each partitioned sub-graph involves generating a container sub-graph and merging the container sub-graph with the partitioned sub-graph to form the merged sub-graph. The container sub-graph may be a modification of the partitioned sub-graph with respect to an identified feature, in some examples.

Abstract: Disclosed are various embodiments related to coordinated monitoring and responding to an emergency situation at a building structure as a supplement to a traditional emergency response. In some embodiments, a system comprises a computing device that is configured to receive sensor data from a sensor network. The sensor network includes monitoring units that monitor various locations of an infrastructure. The computing device determines an occurrence of an emergency event at a location in the infrastructure using an anomaly detector model based at least in part on the sensor data. A hybrid mobile unit is instructed by the computing device to navigate to the location of the emergency event. The hybrid mobile unit is configured to provide mobile sensor data associated with the location to confirm the emergency event.

Abstract: A method and system are directed to testing reconfigurable hardware designs, the method comprising inserting a scan chain into a reconfigurable hardware design associated with an integrated circuit comprising a redacted design; generating, using an automatic test pattern generation (ATPG) system, one or more test patterns and one or more bitstreams; receiving one or more primary outputs and contents of the scan chain from the reconfigurable hardware design by applying the one or more test patterns and the one or more bitstreams to the reconfigurable hardware design based on an ATPG test method of a plurality of ATPG test methods and a test architecture of a plurality of test architectures; comparing the one or more outputs and contents of the scan chain with one or more respective expected outcomes; and determining one or more faults associated with the reconfigurable hardware design based on the comparison.

Abstract: A method and system are directed to generating on-chip bitstreams on reconfigurable hardware. The system comprises a built-in bitstream initialization (BIBI) module configured to generate one or more bitstreams on a semiconductor device. The BIBI module comprising a sequence generator configured to generate a sequence of values for each of the one or more bitstreams, a masking module configured to convert the sequence of values to a given precision of bits, an encryption module configured to apply an encryption scheme to the sequence of values, and an error correction module configured to apply error correction on the sequence of values, wherein the one or more bitstreams are transmitted to a routing network configured to map the one or more bitstreams to input positions of one or more compute blocks.

Abstract: The present disclosure describes various embodiments of systems, apparatuses, and methods for drone-based administration of remotely located devices. One such method comprises deploying an unmanned aerial vehicle from a base station, wherein the base station assigns a maintenance order to the unmanned aerial vehicle for servicing of a remote device, traveling, by the unmanned aerial vehicle, to the location of the remote device, authenticating, by the unmanned aerial vehicle, a valid identification of the remote device; upon the remote device being authenticated by the unmanned aerial vehicle, servicing the remote device by at least charging a power supply of the remote device and transferring contents of a device log to the unmanned aerial vehicle; and after completing the servicing of the remote device; returning to the base station and transferring contents of the device log to the base station.

Abstract: The present disclosure describes systems, apparatuses, and methods for obfuscation-based intellectual property (IP) watermark labeling. One such method comprises identifying, by one or more computing processors, a specific net within an integrated circuit design that is likely to be used in a malicious attack; and adding additional nets to the integrated circuit design that add additional logic states to a finite state machine present in the integrated circuit design. The additional logic states comprise watermarking states for performing authentication of the integrated circuit design, in which a watermark digest can be captured upon application of secret key inputs to the additional nets. Other methods, systems, and apparatuses are also presented.

Abstract: Various embodiments of the present disclosure provide a scan-based architecture for register-transfer-level (RTL) or gate-level designs that improves the security of scan chain-based design-for-testability (DFT) structures. In various embodiments, the scan-based architecture includes invisible scan chains that are hidden in such a way that an attacker cannot easily identify or locate the invisible scan chains for exploitation and revealing internal secure information of the design. The invisible scan chains are dynamically configurable into a scan chain with select flip-flops, such that scan paths of the invisible scan chains may be different between different designs, chips, or testing operations. Various embodiments further employ key-based obfuscation by combining a scan control finite state machine with existing state machines within a design, which improves design security against unauthorized use and increases confidentiality.

Abstract: A computing entity comprising an intelligent digital memory system and one or more processors communicatively coupled to the intelligent digital memory system is provided. The one or more processors configured to receive one or more storage parameters, determine a store procedure cue neuron search location from candidate ones of a plurality of cue neurons associated with a neural memory network (NoK), insert the input data as a data neuron into the NoK based on the store procedure cue neuron search location, temporally link the data neuron with a location of last insertion, and modify the NoK in a manner of accessibility based on a pattern of a search for the store procedure cue neuron search location.

Abstract: A system for secure testing and provisioning of an integrated circuit (IC) includes, in part, a secure reconfigurable key provisioning architecture (SLEEVE) module disposed in the IC, and a secure asset provisioning hardware entity (SAPHE) module. The IC may include, in part, a modified IEEE 1500 wrapper to control its operation modes. The SLEEVE module may include, in part, an encoding/decoding module and an unlocking module. The encoding/decoding module may include, in part, a decode key stream cipher module, an encode key stream cipher module, Seed Key programmable linear-feedback shift registers (LFSRs), Initialization Vector (IV) LFSRs, and configuration registers. The encoding/decoding module may be configured to generate key bits for decoding and encoding inputs and outputs of the IC. The unlocking module may include, in part, a pattern matching block and a counter. The unlocking module may be configured to enable write access to the configuration registers.

Abstract: Apparatus, systems, and methods described herein relate generally to autonomous mobile units carrying a modular configurable battery system that may attach and power mobile units in transportation systems. A method can include determining charge levels, current positions, and transport speeds for an electric vehicle (EV), identifying one or more EVs in need of charging, and mobilizing a Mobile Charging Station (MoCS) to deliver one or more external batteries. A processor, with a memory including computer program code, can be configured to receive current charge level data for mobile battery-powered entities, identify one or more EVs to be charged and the proximity of both MoCS and physical battery stations, and send charging instructions to the EVs. A routing and charge transaction scheduling algorithm can be used to optimize the route of one or more battery-powered entities and to schedule charge transactions between the EV and MoCS and/or the battery station.

Abstract: A method for fabricating nano-electro-mechanical tags for identification and authentication includes, in part, forming a protective layer above a substrate, forming a first conductive layer above the protective layer serving as a first electrode, forming a piezoelectric layer above the first conductive layer, forming a second conductive layer above the piezoelectric layer, patterning the second conductive layer to form a second electrode, patterning the piezoelectric layer to expose one or more portions of the first conductive layer, and forming one or more trenches that extends into a plurality layers formed above. In addition, a sacrificial layer can be formed above portions of the substrate, and the sacrificial layer can be removed by etching to release the nano-electro-mechanical tags from the substrate.

Abstract: An integrated circuit includes, in part, a key management unit configured to generate a seeding key during a start-up phase, an encryption module configured to encrypt data using the seeding key and deliver the encrypted data to a second integrated circuit, and an encoder configured to encode the seeding key and deliver the encoded seeding key to the second IC. The second integrated circuit includes, in part, a decoder configured to decode the seeding key. Each of the integrated circuits further includes, in part, a linear-feedback shift register that receives the same clock signals and loads the seeding key.