Patents by Inventor Swarup Bhunia

Swarup Bhunia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210284043
    Abstract: Apparatus, systems, and methods described herein relate generally to on-the-go entity-to-entity charging for multi-level battery-powered entities in transportation systems. A method can include determining charge levels, current positions, battery configuration, and transport speeds for an electric vehicle (EV), identifying one or more EVs in need of charging, and mobilizing a nearby EV for on-the-go peer-to-peer charging. A processor, with a memory including computer program code, can be configured to receive current charge level data for mobile battery-powered entities, identify one or more EVs to be charged and one or more other EVs that have excess charge to transfer, and send charging instructions to the EVs. A routing and charge transaction scheduling algorithm can be used to optimize the route of one or more battery-powered entities and to schedule charge transactions between EVs and/or a charging entity. A heuristic battery architecture compiler can be used to optimize battery architecture.
    Type: Application
    Filed: March 5, 2021
    Publication date: September 16, 2021
    Inventors: Shuo WANG, Swarup BHUNIA, Prabuddha CHAKRABORTY, Robert PARKER, Rohan Reddy Kalavakonda
  • Publication number: 20210221675
    Abstract: A method for fabricating nano-electro-mechanical tags for identification and authentication includes, in part, forming a protective layer above a substrate, forming a first conductive layer above the protective layer serving as a first electrode, forming a piezoelectric layer above the first conductive layer, forming a second conductive layer above the piezoelectric layer, patterning the second conductive layer to form a second electrode, patterning the piezoelectric layer to expose one or more portions of the first conductive layer, and forming one or more trenches that extends into a plurality layers formed above. In addition, a sacrificial layer can be formed above portions of the substrate, and the sacrificial layer can be removed by etching to release the nano-electro-mechanical tags from the substrate.
    Type: Application
    Filed: January 19, 2021
    Publication date: July 22, 2021
    Inventors: Roozbeh Tabrizian, Swarup Bhunia
  • Publication number: 20210225039
    Abstract: A joint compression and encryption system is configured to retrieve, from a local memory or image capture device, an image file including a first plurality of segments. The system is further configured to identify, for one or more segment of the first plurality of segments, a matching segment in a local segmentation repository. The system is further configured to compress remaining segments of the first plurality of segments for which no matching segment was identified into a compressed remaining segment set. The system is further configured to transmit, via an unsecure communication channel and to a second computing entity, the identifications of the matching segments, and the compressed remaining segment set. The system is further configured to, prior to retrieving the image file, perform a handshake or calibration process. The system is further configured to encrypt the matching segments using a key into an encrypted segment set and transmit the key to the second computing entity.
    Type: Application
    Filed: January 21, 2021
    Publication date: July 22, 2021
    Inventors: Swarup Bhunia, Prabuddha Chakraborty, Jonathan William Cruz, Tamzidul Hoque, Toan Trung Nguyen
  • Publication number: 20210192018
    Abstract: The present disclosure describes exemplary methods and systems of protecting an integrated circuit. One exemplary method comprises receiving a plurality of key inputs for enabling operation of the integrated circuit; determining whether the received key inputs are correct key inputs for enabling operation of the integrated circuit; and if the received key inputs are determined to be incorrect key inputs, locking sequential logic and combinational logic of the integrated circuit until correct key inputs are received.
    Type: Application
    Filed: December 14, 2020
    Publication date: June 24, 2021
    Inventors: SWARUP BHUNIA, MD MOSHIUR RAHMAN, ABDULRAHMAN ALAQL
  • Publication number: 20210173963
    Abstract: Embodiments of the present disclosure provide methods, apparatus, systems, computer program products, computing devices, and/or computing entities for obfuscating a hardware intellectual property (IP) design by locking the design based at least in part on a plurality of key-bits. In one embodiment, a method is provided comprising: generating a key vulnerability matrix for a locked version of the design and a plurality of attacks that comprises for each attack, a vector comprising a value for each key-bit identifying whether the attack successfully extracted a correct key value for the key-bit; and for each key-bit: determining whether the key-bit is vulnerable to an attack based on the values in the matrix; and responsive to being vulnerable: identifying a set of solutions to mitigate the attack; selecting a solution from the set; and inserting a key-gate type for the key-bit at a location identified by the selected solution into the design.
    Type: Application
    Filed: November 23, 2020
    Publication date: June 10, 2021
    Inventors: Abdulrahman Alaql, Saranyu Chattopadhyay, Swarup Bhunia, Prabuddha Chakraborty
  • Patent number: 11017125
    Abstract: Novel methods of virtualization with unique virtual architectures on field-programmable gate arrays (FPGAs) are provided. A hardware security method can include providing one or more field-programmable gate arrays (FPGAs), and creating an application specialized virtual architecture (or overlay) over the one or more FPGAs (for example, by providing an overlay generator). Unique bitfiles that configure the overlays implemented on the FPGAs can be provided for each deployed FPGA. The application specialized virtual architecture can be constructed using application code, or functions from a domain, to create an overlay represented by one or more hardware description languages (e.g., VHDL).
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: May 25, 2021
    Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INCORPORATED
    Inventors: Greg M. Stitt, Kai Yang, Swarup Bhunia, Robert A. Karam
  • Publication number: 20210148977
    Abstract: The present disclosure describes exemplary methods and systems that are applicable for hardware authentication, counterfeit detection, and in-field tamper detection in both printed circuit board and/or integrated circuit levels by utilizing random variations in boundary-scan path delay and/or current in the industry-standard JTAG-based design-for-test structure to generate unique device identifiers.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 20, 2021
    Inventors: SWARUP BHUNIA, SHUBHRA DEB PAUL
  • Publication number: 20210097220
    Abstract: Embodiments of the present disclosure provide methods, apparatus, and computer program products for generating an insertion netlist for a target circuit configured for inserting a malicious design alteration into the circuit based on a design identifying reference trigger nets. Features are extracted for each net identified in a netlist for the circuit. A set of reference trigger features is generated for each of the reference trigger nets. A net is selected from the netlist for each set of reference trigger features based on a similarity between the features of the net and the set of reference trigger features. The insertion netlist is generated that includes the circuit with the malicious design alteration inserted at each of the selected nets.
    Type: Application
    Filed: September 29, 2020
    Publication date: April 1, 2021
    Inventors: Swarup Bhunia, Prabuddha Chakraborty, Abhiskek A. Nair, Tamzidul Hoque, Jonathan W. Cruz, Naren Masna, Pravin Gaikwad
  • Publication number: 20200380868
    Abstract: Various examples are provided related to multi-purpose context-aware bumps (CABs) that can support dynamic adaptation of form factors and functionality. In one example, a CAB system can include sensors distributed in a traffic network and communicatively coupled to a remotely located computing environment; context-aware bumps (CABs) placed in the traffic network and communicatively coupled to the remotely located computing environment; and a CAB application configured to adjust a form factor of a CAB in response to information obtained from the sensors and/or CABs. In another example, a method can include receiving, by a remotely located computing environment, traffic information from sensors distributed in a traffic network or CABs placed in the traffic network; communicating, by the remotely located computing environment, a form factor control to a CAB in response to the traffic information; and adjusting a form factor of the CAB in response to the form factor control.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 3, 2020
    Inventors: Swarup Bhunia, Prabuddha Chakraborty, Lili Du, Sandip Ray
  • Patent number: 10837926
    Abstract: An example includes performing near infra-red (NIR) spectrometry to provide NIR measurement data for a sample compound. The method also includes performing magnetic resonance (MR) spectrometry to provide MR measurement data for the sample compound. The method also includes analyzing, by a computing device, the MR measurement data in view of the NIR measurement data to characterize the sample compound.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: November 17, 2020
    Assignees: CASE WESTERN RESERVE UNIVERSITY, UNIVERSITY OF FLORIDA RESEARCH FOUNDATION
    Inventors: Soumyajit Mandal, Swarup Bhunia, Naren Vikram Raj Masna, Cheng Chen, Mason Greer, Fengchao Zhang
  • Publication number: 20200302064
    Abstract: A method and system for evaluating software tools that detect malicious hardware modifications is provided. In one embodiment, among others, a system comprises a computing device and an application. The application causes the computing device to at least receive hardware description language code that represents a circuit design and calculate a signal probability for one or more nodes in the circuit design. The application also causes the computing device to identify one or more rare nodes in the circuit design and generate a Trojan sample population. The application further causes the computing device to generate a feasible Trojan population and generate a Trojan test instance based at least in part on a random selection from the Trojan feasible population. Additionally, the application causes the computing device to generate modified hardware description code from the Trojan test instance.
    Type: Application
    Filed: March 20, 2019
    Publication date: September 24, 2020
    Inventors: Swarup Bhunia, Jonathan William Cruz, Prabhat Kumar Mishra
  • Publication number: 20200293730
    Abstract: This disclosure relates to tagging of materials and objects and analysis for authentication thereof. An example method includes analyzing separately a number of locations distributed across a given surface of a solid object according to one or more analysis technologies to determine feature data for each of the locations. The feature data are indicative of a respective chemical property and/or mechanical property of the solid object at each of the locations, corresponding to a feature tag, and the feature data depend on the one or more analysis technologies. The method also includes determining a tag signature for the solid object based on the feature data determined for each of the locations.
    Type: Application
    Filed: March 12, 2020
    Publication date: September 17, 2020
    Inventors: Swarup Bhunia, Naren Vikram Masna, Soumyajit Mandal
  • Publication number: 20200262305
    Abstract: Apparatus, systems, and methods described herein relate generally to on-the-go entity-to-entity charging in transportation systems. A method can include determining charge levels, current positions, and transport speeds for an electric vehicle (EV), identifying one or more EVs in need of charging, and mobilizing a nearby EV for on-the-go peer-to-peer charging. A processor, with a memory including computer program code, can be configured to receive current charge level data for mobile battery-powered entities, identify one or more EVs to be charged and one or more other EVs that have excess charge to transfer, and send charging instructions to the EVs. A routing and charge transaction scheduling algorithm can be used to optimize the route of one or more battery-powered entities and to schedule charge transactions between EVs and/or a charging entity.
    Type: Application
    Filed: February 5, 2020
    Publication date: August 20, 2020
    Inventors: Prabuddha CHAKRABORTY, Swarup BHUNIA
  • Patent number: 10586135
    Abstract: Data is encoded for identification and labeling using a multitude of nano-electro-mechanical structures formed on a substrate. The number of such structures, their shapes, choice of materials, the spacing therebetween and the overall distribution of the structures result in a vibrational pattern or an acoustic signature that uniquely corresponds to the encoded data. A first group of the structures is formed in conformity with the design rules of a fabrication process used to manufacture the device that includes the structures. A second group of the structures is formed so as not to conform to the design rules and thereby to undergo variability as a result of the statistical variations that is inherent in the fabrication process.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: March 10, 2020
    Assignee: University of Florida Research Foundation, Incorporated
    Inventors: Roozbeh Tabrizian, Swarup Bhunia
  • Patent number: 10521600
    Abstract: Aspects of system-on-chip (SoC) security architecture that supports systematic and efficient implementation, validation, and in-field upgrade of security policies are described. In one example, an apparatus can include at least one intellectual property (IP) core, a centralized reconfigurable security policy engine (RSPE) and at least one security wrapper. The RSPE implements actionable constraint based on a security policy and at least one event frame. A security wrapper is associated with an IP core. The security wrapper is configured to communicate an event frame to the RSPE in response to an event.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: December 31, 2019
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Swarup Bhunia, Atul Prasad Deb Nath
  • Patent number: 10478113
    Abstract: The present disclosure relates generally to using detected bladder events for the diagnosis of urinary incontinence or the treatment of lower urinary tract dysfunction. A system includes a sensing device comprising a pressure sensor to directly detect a pressure within a bladder. The sensing device is adapted to be located within the bladder. The system also includes a signal processing device to: receive a signal indicating the detected pressure within the bladder; detect a bladder event based the detected pressure within the signal; and characterize the bladder event as a bladder contraction event or a non-contraction event. The characterization of the bladder event can be used in the diagnosis of urinary incontinence or the treatment of lower urinary tract dysfunction.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: November 19, 2019
    Assignees: THE CLEVELAND CLINIC FOUNDATION, CASE WESTERN RESERVE UNIVERSITY, THE U.S. GOV'T AS REPRESENTED BY THE DEPT OF VETERANS AFFAIRS
    Inventors: Margot S. Damaser, Swarup Bhunia, Robert Karam, Steve Majerus, Dennis Bourbeau, Hui Zhu
  • Publication number: 20190305927
    Abstract: A technique to generate node locked bitstreams for FPGAs to simultaneously protect against malicious reconfiguration as well as FPGA IP piracy is provided. According to some aspects, modifications in FPGA architecture along with an associated mapping flow enable authenticating and programming a device in a way that maintains FPGA security while requiring low overhead. The technique is more robust against side channel and destructive reverse-engineering attacks in comparison with key-based encryption methods, and has less area, power, and latency overhead. The node locked bitstream approach is attractive in many existing and emerging applications including IoTs, which may require field upgrade of FPGA.
    Type: Application
    Filed: March 17, 2017
    Publication date: October 3, 2019
    Inventors: Swarup Bhunia, Robert A. Karam, Tamzidul Hoque
  • Publication number: 20190223775
    Abstract: The present disclosure relates generally to using detected bladder events for the diagnosis of urinary incontinence or the treatment of lower urinary tract dysfunction. A system includes a sensing device comprising a pressure sensor to directly detect a pressure within a bladder. The sensing device is adapted to be located within the bladder. The system also includes a signal processing device to: receive a signal indicating the detected pressure within the bladder; detect a bladder event based the detected pressure within the signal; and characterize the bladder event as a bladder contraction event or a non-contraction event. The characterization of the bladder event can be used in the diagnosis of urinary incontinence or the treatment of lower urinary tract dysfunction.
    Type: Application
    Filed: March 21, 2019
    Publication date: July 25, 2019
    Inventors: Margot S. Damaser, Swarup Bhunia, Robert Karam, Steve Majerus, Dennis Bourbeau, Hui Zhu
  • Publication number: 20190188546
    Abstract: Data is encoded for identification and labeling using a multitude of nano-electro-mechanical structures formed on a substrate. The number of such structures, their shapes, choice of materials, the spacing therebetween and the overall distribution of the structures result in a vibrational pattern or an acoustic signature that uniquely corresponds to the encoded data. A first group of the structures is formed in conformity with the design rules of a fabrication process used to manufacture the device that includes the structures. A second group of the structures is formed so as not to conform to the design rules and thereby to undergo variability as a result of the statistical variations that is inherent in the fabrication process.
    Type: Application
    Filed: June 18, 2018
    Publication date: June 20, 2019
    Inventors: Roozbeh Tabrizian, Swarup Bhunia
  • Publication number: 20190180041
    Abstract: Aspects of system-on-chip (SoC) security architecture that supports systematic and efficient implementation, validation, and in-field upgrade of security policies are described. In one example, an apparatus can include at least one intellectual property (IP) core, a centralized reconfigurable security policy engine (RSPE) and at least one security wrapper. The RSPE implements actionable constraint based on a security policy and at least one event frame. A security wrapper is associated with an IP core. The security wrapper is configured to communicate an event frame to the RSPE in response to an event.
    Type: Application
    Filed: December 13, 2017
    Publication date: June 13, 2019
    Inventors: Swarup Bhunia, Atul Prasad Deb Nath