Patents by Inventor Swarup Bhunia

Swarup Bhunia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190188546
    Abstract: Data is encoded for identification and labeling using a multitude of nano-electro-mechanical structures formed on a substrate. The number of such structures, their shapes, choice of materials, the spacing therebetween and the overall distribution of the structures result in a vibrational pattern or an acoustic signature that uniquely corresponds to the encoded data. A first group of the structures is formed in conformity with the design rules of a fabrication process used to manufacture the device that includes the structures. A second group of the structures is formed so as not to conform to the design rules and thereby to undergo variability as a result of the statistical variations that is inherent in the fabrication process.
    Type: Application
    Filed: June 18, 2018
    Publication date: June 20, 2019
    Inventors: Roozbeh Tabrizian, Swarup Bhunia
  • Publication number: 20190180041
    Abstract: Aspects of system-on-chip (SoC) security architecture that supports systematic and efficient implementation, validation, and in-field upgrade of security policies are described. In one example, an apparatus can include at least one intellectual property (IP) core, a centralized reconfigurable security policy engine (RSPE) and at least one security wrapper. The RSPE implements actionable constraint based on a security policy and at least one event frame. A security wrapper is associated with an IP core. The security wrapper is configured to communicate an event frame to the RSPE in response to an event.
    Type: Application
    Filed: December 13, 2017
    Publication date: June 13, 2019
    Inventors: Swarup Bhunia, Atul Prasad Deb Nath
  • Patent number: 10283459
    Abstract: A semiconductor device can include a first metal trace, a first via disposed on the first metal trace, a second metal trace disposed on the first via, and an insulator interposed between the first metal trace and the first via. The insulator can be configured to lower an energy barrier or redistribute structure defects or charge carriers, such that the first metal trace and the first via are electrically connected to each other when power is applied. The semiconductor device can further include a dummy via disposed on the first metal trace.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: May 7, 2019
    Assignee: University of Florida Research Foundation, Incorporated
    Inventors: Swarup Bhunia, Haoting Shen, Mark M. Tehranipoor, Domenic J. Forte, Navid Asadizanjani
  • Publication number: 20190072506
    Abstract: An example includes performing near infra-red (NIR) spectrometry to provide NIR measurement data for a sample compound. The method also includes performing magnetic resonance (MR) spectrometry to provide MR measurement data for the sample compound. The method also includes analyzing, by a computing device, the MR measurement data in view of the NIR measurement data to characterize the sample compound.
    Type: Application
    Filed: September 4, 2018
    Publication date: March 7, 2019
    Inventors: Soumyajit Mandal, Swarup Bhunia, Naren Vikram Raj Masna, Cheng Chen, Mason Greer, Fengchao Zhang
  • Patent number: 10216965
    Abstract: This disclosure describes techniques for generating physically unclonable functions (PUF) from non-volatile memory cells. The PUFs leverage resistance variations in non-volatile memory cells. Resistance variations in array of non-volatile memory cells may be produce a bitstring during an enrollment process. The bitstring may be stored in the non-volatile memory array. Regeneration may include retrieving the bitstring from the non-volatile memory array.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: February 26, 2019
    Assignee: STC.UNM
    Inventors: James Plusquellic, Swarup Bhunia
  • Publication number: 20180197828
    Abstract: A semiconductor device can include a first metal trace, a first via disposed on the first metal trace, a second metal trace disposed on the first via, and an insulator interposed between the first metal trace and the first via. The insulator can be configured to lower an energy barrier or redistribute structure defects or charge carriers, such that the first metal trace and the first via are electrically connected to each other when power is applied. The semiconductor device can further include a dummy via disposed on the first metal trace.
    Type: Application
    Filed: January 5, 2018
    Publication date: July 12, 2018
    Inventors: Swarup Bhunia, Haoting Shen, Mark M. Tehranipoor, Domenic J. Forte, Navid Asadizanjani
  • Publication number: 20180165478
    Abstract: Novel methods of virtualization with unique virtual architectures on field-programmable gate arrays (FPGAs) are provided. A hardware security method can include providing one or more field-programmable gate arrays (FPGAs), and creating an application specialized virtual architecture (or overlay) over the one or more FPGAs (for example, by providing an overlay generator). Unique bitfiles that configure the overlays implemented on the FPGAs can be provided for each deployed FPGA. The application specialized virtual architecture can be constructed using application code, or functions from a domain, to create an overlay represented by one or more hardware description languages (e.g., VHDL).
    Type: Application
    Filed: December 12, 2017
    Publication date: June 14, 2018
    Inventors: Greg M. Stitt, Kai Yang, Swarup Bhunia, Robert A. Karam
  • Patent number: 9685958
    Abstract: A locking system for an integrated circuit (IC) chip can include an arrangement of one or more antifuse devices in a signal path of the IC chip. The antifuse devices can be configured to operate in a first state, corresponding to a normally open switch, to inhibit normal operation of the IC chip, and to transition from the first state to a permanent second state, corresponding to a closed switch, in response to a program signal applied to at least one terminal of the IC chip to enable the normal operation of the IC chip.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: June 20, 2017
    Assignee: Case Western Reserve University
    Inventors: Swarup Bhunia, Abhishek Basak, Yu Zheng
  • Patent number: 9628086
    Abstract: An antifuse apparatus can include a cantilever extending from a first electrode portion to terminate in a distal end. A second electrode portion can be spaced apart from the cantilever by an air gap. In response to a program voltage across the first and second electrode portions, the cantilever can be adapted to move from an unprogrammed condition, corresponding to an open circuit condition where the cantilever is spaced apart from the second electrode portion, to at least one permanent programmed condition, corresponding to a short circuit condition between the first and second electrode portions where the cantilever engages the second electrode portion.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: April 18, 2017
    Assignee: Case Western Reserve University
    Inventors: Ting He, Fengchao Zhang, Swarup Bhunia, Philip X. -L. Feng
  • Publication number: 20160354028
    Abstract: The present disclosure relates generally to using detected bladder events for the diagnosis of urinary incontinence or the treatment of lower urinary tract dysfunction. A system includes a sensing device comprising a pressure sensor to directly detect a pressure within a bladder. The sensing device is adapted to be located within the bladder. The system also includes a signal processing device to: receive a signal indicating the detected pressure within the bladder; detect a bladder event based the detected pressure within the signal; and characterize the bladder event as a bladder contraction event or a non-contraction event. The characterization of the bladder event can be used in the diagnosis of urinary incontinence or the treatment of lower urinary tract dysfunction.
    Type: Application
    Filed: April 29, 2016
    Publication date: December 8, 2016
    Inventors: Margot S. Damaser, Swarup Bhunia, Robert Karam, Steve Majerus, Dennis Bourbeau, Hui Zhu
  • Publication number: 20160328578
    Abstract: This disclosure describes techniques for generating physically unclonable functions (PUF) from non-volatile memory cells. The PUFs leverage resistance variations in non-volatile memory cells. Resistance variations in array of non-volatile memory cells may be produce a bitstring during an enrollment process. The bitstring may be stored in the non-volatile memory array. Regeneration may include retrieving the bitstring from the non-volatile memory array.
    Type: Application
    Filed: December 23, 2014
    Publication date: November 10, 2016
    Inventors: James Plusquellic, Swarup Bhunia
  • Publication number: 20160047855
    Abstract: This disclosure relates generally to printed circuit board authentication, such as for protecting printed circuit boards against counterfeiting. The authentication can be implemented based on measurements from the PCB used to generate a unique signature for the PCB. The generated signature of the PCB can be evaluated to determine if the PCB is authentic or counterfeit.
    Type: Application
    Filed: August 17, 2015
    Publication date: February 18, 2016
    Inventors: Swarup Bhunia, Fengchao Zhang, Yu Zheng, Andrew Hennessy
  • Publication number: 20150130506
    Abstract: A locking system for an integrated circuit (IC) chip can include an arrangement of one or more antifuse devices in a signal path of the IC chip. The antifuse devices can be configured to operate in a first state, corresponding to a normally open switch, to inhibit normal operation of the IC chip, and to transition from the first state to a permanent second state, corresponding to a closed switch, in response to a program signal applied to at least one terminal of the IC chip to enable the normal operation of the IC chip.
    Type: Application
    Filed: November 14, 2014
    Publication date: May 14, 2015
    Inventors: Swarup Bhunia, Abhishek Basak, Zheng Yu
  • Publication number: 20150130509
    Abstract: An antifuse apparatus can include a cantilever extending from a first electrode portion to terminate in a distal end. A second electrode portion can be spaced apart from the cantilever by an air gap. In response to a program voltage across the first and second electrode portions, the cantilever can be adapted to move from an unprogrammed condition, corresponding to an open circuit condition where the cantilever is spaced apart from the second electrode portion, to at least one permanent programmed condition, corresponding to a short circuit condition between the first and second electrode portions where the cantilever engages the second electrode portion.
    Type: Application
    Filed: November 14, 2014
    Publication date: May 14, 2015
    Inventors: Ting He, Fengchao Zhang, Swarup Bhunia, Philip X.-L. Feng
  • Patent number: 8402401
    Abstract: One embodiment provides a method for protecting an integrated circuit chip design. The method can include storing in memory a circuit description of an integrated circuit core comprising a set of nodes and selecting a plurality of modification nodes from the set of nodes. A sequential structure can be inserted into the circuit description to provide a modified circuit description, the sequential structure utilizing the plurality of modification nodes as inputs. The modified circuit description can be stored in memory.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: March 19, 2013
    Assignee: Case Western University
    Inventors: Rajat Subhra Chakraborty, Seetharam Narasimhan, Swarup Bhunia
  • Publication number: 20110113392
    Abstract: One embodiment provides a method for protecting an integrated circuit chip design. The method can include storing in memory a circuit description of an integrated circuit core comprising a set of nodes and selecting a plurality of modification nodes from the set of nodes. A sequential structure can be inserted into the circuit description to provide a modified circuit description, the sequential structure utilizing the plurality of modification nodes as inputs. The modified circuit description can be stored in memory.
    Type: Application
    Filed: November 9, 2010
    Publication date: May 12, 2011
    Inventors: RAJAT SUBHRA CHAKRABORTY, Seetharam Narasimhan, Swarup Bhunia
  • Patent number: 7548473
    Abstract: A test circuit used for determining a fault in a memory device. The test circuit includes a read circuit configured to read memory cell contents in a memory device at a first time instant and second time instant. The test circuit includes a comparator that compares the contents at the first and second time instants. If the contents are different from one another, the comparator indicates that a fault has occurred. Test methods are also used to determine if a fault has occurred in a memory cell.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: June 16, 2009
    Assignee: Purdue Research Foundation
    Inventors: Qikai Chen, Swarup Bhunia, Hamid Mahmoodi, Kaushik Roy
  • Patent number: 7454738
    Abstract: A logic synthesis method to apply supply gating to idle portions of general logic circuits in their active mode of operation to reduce power requirements and the circuits resulting therefrom. A Shannon expansion is utilized to determine idle portions and active portions of the general logic circuits.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: November 18, 2008
    Assignee: Purdue Research Foundation
    Inventors: Swarup Bhunia, Nilanjan Banerjee, Hamid Mahmoodi, Qikai Chen, Kaushik Roy
  • Patent number: 7319343
    Abstract: A circuit includes an input block and a combinational logic block. The input block has reconfigurable latches that are connected serially during testing times such that an output of one of the latches is connected to an input of a successive latch. The latches are directly connected to first level gates of the combinational logic block. The combinational logic block contains switches that prevent the propagation of signals through the combinational logic block during testing times other than when a desired vector is loaded into the latches. The switches disconnect the power and/or ground from the first level gates. The switches further connect the outputs of the first level gates to power or ground, depending on the type of transistors used in the first level gates. The switches alternatively delay the output through a pair of inverters and resupply the output to itself if refreshing the output is desired.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: January 15, 2008
    Assignee: Purdue Research Foundation - Purdue University
    Inventors: Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowhury, Saibal Mukhopadhyay, Kaushik Roy
  • Publication number: 20070242538
    Abstract: A test circuit used for determining a fault in a memory device. The test circuit includes a read circuit configured to read memory cell contents in a memory device at a first time instant and second time instant. The test circuit includes a comparator that compares the contents at the first and second time instants. If the contents are different from one another, the comparator indicates that a fault has occurred. Test methods are also used to determine if a fault has occurred in a memory cell.
    Type: Application
    Filed: April 14, 2006
    Publication date: October 18, 2007
    Inventors: Qikai Chen, Swarup Bhunia, Hamid Mahmoodi, Kaushik Roy