Abstract: A data reading method for motion estimation in a video processing chipset is provided. The video processing chipset is coupled to an external memory device, wherein a first frame is stored in the external memory device. In the data reading method, a second frame is first divided into M×N sub frame sets, wherein each of the sub frame sets includes O×P sub frames. Then, each of the sub frame sets is selected in a calculation sequence, wherein the selected sub frame set is stored into an internal memory. Next, a predicted search path of each sub frame in the selected sub frame set is calculated. Thereafter, a predicted reading range is determined, wherein the predicted reading range includes the predicted search paths of the sub frames. Finally, a comparison data is read from the first frame according to the predicted reading range.

Abstract: A data reading method for motion estimation in an embedded system is provided. The embedded system includes an external memory device and a video encoding device, wherein the external memory device stores a first frame, and the video encoding device has an internal memory. First, a second frame is divided into M×N sub frame sets, wherein each of the sub frame sets has O×P sub frames. Then, each of the sub frame sets is selected in a calculation sequence, and the selected sub frame set is stored into the internal memory. Next, a predicted search path of each sub frame in the selected sub frame set is calculated. Thereafter; a predicted reading range is determined, wherein the predicted reading range includes the predicted search paths of the sub frames. Finally, a comparison data is read from the first frame according to the predicted reading range.

Abstract: A method for performing motion estimation is provided. The method includes the following steps: selecting a current block in a current frame; obtaining motion vectors and residual data of a plurality of neighboring blocks adjacent to the current block; setting a predetermined threshold value according to the residual data of the plurality of neighboring blocks; comparing the current block with an initial reference block in a reference frame to obtain an initial comparison result, and comparing the predetermined threshold value with the initial comparison result; determining a predicted motion vector of the current block according to the motion vectors of the plurality of neighboring blocks if the initial comparison result is larger than the predetermined threshold value; and performing a block-matching operation in a search window corresponding to the predicted motion vector to determine a corresponding reference block which best matches the current block.

Abstract: Methods, software tools and systems for analyzing software applications, e.g., Web applications, are described. A software application to be analyzed is transformed into an abstract representation which preserves its information flow properties. The abstract interpretation is evaluated to identify vulnerabilities using, for example, type qualifiers to associate security levels with variables and/or functions in the application being analyzed and typestate checking. Runtime guards are inserted into the application to secure identified vulnerabilities.

Abstract: A method for performing motion estimation is provided. The method includes the following steps: selecting a current block in a current frame; comparing the current block with an initial reference block in a reference frame to obtain an initial comparison parameter, wherein position of the initial reference block in the reference frame is corresponding to position of the current block in the current frame; determining a predicted search window corresponding to the current block based on the initial comparison parameter; and comparing the current block with reference blocks in the predicted search window to obtain comparison parameters respectively, whereby a best-match reference block in the predicted search window is determined.

Abstract: The invention provides DC-DC converters comprising a load sensor, a variable Power MOS, and a Power MOS width controlling and driving device. The Power MOS width controlling and driving device is coupled between the load sensor and the variable Power MOS. The variable Power MOS comprises a plurality of PMOS transistors coupled in parallel and a plurality of NMOS transistors coupled in parallel. After the load sensor detects the load current of the DC-DC converter, the Power MOS width controlling and driving device conducts the PMOS and NMOS transistors according to the sensed load current to control the total size of the conduction paths that couple a transformed DC voltage output terminal to a source of an original DC voltage or ground.

Abstract: A method of an efficient adaptive mode selection for H.264/AVC-coded video delivery in burst-packet-loss networks to generate the image data of the missing macroblocks in the decoded current frame by using the information related to the spatial redundancy in the same frame and the temporal redundancy in the inter frames is disclosed. The method first employs the Intra High-Speed Spatial Error Concealment (SEC) method for the initial frame. For the succeeding inter frames, the Temporal Error Concealment (TEC) method is used when the Adjacent External Boundary Matching Error (AEBME) of the surrounding macroblocks is not more than the dynamic threshold (DT?). The Intra High-Speed SEC is used when AEBME is more than (DT?) and the surrounding macroblocks are all coded intra-method, otherwise the task proceeds by employing Normal SEC.

Abstract: A monitor device, a monitor method and a computer program product thereof for hardware are disclosed. The hardware comprises a central processing unit (CPU) and a storage module. The monitor device comprises a retrieval module and an analysis module. The retrieval module is configured to retrieve the entry point information of a process before the process is executed, wherein the process comprises at least one instruction from the hardware. The analysis module is configured to retrieve an address corresponding to the process according to the entry point information. When the CPU executes the at least one instruction, the storage module records the at least one instruction according to the address.

Abstract: A method of fast motion estimation in VLSI architecture with low-power and high-throughput for multimedia System-on-Chip design is disclosed. The method uses the data prediction and data reuse technique to find out the best matching block within the search range of the reference frame for the target block in the current frame in order to obtain the respective motion vector. The external memory bandwidth and the internal memory size in the video coding system are significantly reduced so as to speed up the process of motion estimation and most of the power consumption for the motion estimation process is further saved in the embedded video coding systems.

Abstract: A high-performance block-matching VLSI architecture with low memory bandwidth for power-efficient multimedia devices is disclosed. The architecture uses several current blocks with the same spatial address in different current frames to search the best matched blocks in the search window of the reference frame based on the best matching algorithm (BMA) to implement the process of motion estimation in video coding. The scheme of the architecture using several current blocks for one search window greatly increases data reuse, accelerates the process of motion estimation, and reduces the data bandwidth and the power consumption.

Abstract: A spatial error concealment (SEC) method for concealing a spatial image error of an encoded image frame caused by a damaged macroblock (MB) is provided. The SEC method selects a proper SEC algorithm by adaptively classifying a plurality of correct MBs adjacent to the damaged MB, so as to execute interpolation pixel compensation or matching block copying, thus obtaining image data of the damaged MB. In such a way, the damaged MB is processed to apply the least affection to the entire image frame. The SEC algorithm is selected from bilinear interpolation (BI) method, directional interpolation (DI) method, multi-directional interpolation (MDI) method, and best neighborhood matching (BNM) method. The SEC method further includes a fast determination calculation, which utilizes image directional data related to the damaged MB in coding data of the original frame to execute a direct SEC process, for saving time on determination calculation, thus accelerating the processing speed.

Abstract: A method of temporal error concealment for generating the image data of the missing macro-blocks in the current frame by using the previous frame and the correct data of the current frame is disclosed. The method includes the steps: first using Optimal Regression Plane to estimate the space motion vectors for each block in the missing macro-blocks; selecting appropriate motion vectors from the estimated space motion vectors and the correct temporal motion vectors in the pervious frame as the candidate motion vectors; dividing the missing macro-block into sub-blocks with optimal size; fine tuning the candidate motion vectors as the predicted motion vectors; and using the predicted motion vectors to generate the predicted image data for the missing macro-block and further concealing the effect of the missing macro-blocks upon the image quality of the current frame. The method reduces the computation time, speeds up the process, and improves the image quality.

Abstract: The invention provides DC-DC converters comprising a load sensor, a variable Power MOS, and a Power MOS width controlling and driving device. The Power MOS width controlling and driving device is coupled between the load sensor and the variable Power MOS. The variable Power MOS comprises a plurality of PMOS transistors coupled in parallel and a plurality of NMOS transistors coupled in parallel. After the load sensor detects the load current of the DC-DC converter, the Power MOS width controlling and driving device conducts the PMOS and NMOS transistors according to the sensed load current to control the total size of the conduction paths that couple a transformed DC voltage output terminal to a source of an original DC voltage or ground.

Abstract: The invention discloses DC-DC converters comprising an inductance, a pulse width modulator generating a pulse signal according to the voltage level of a transformed voltage output terminal, a load sensor sensing a load current, an adaptive enable signal generator generating a PMOS transistor enable signal and an NMOS transistor enable signal based on the pulse signal and the load current, and a power transistor set comprising at least one PMOS transistor and an NMOS transistor. The power transistor set is used in coupling the transformed voltage output terminal to an original DC voltage source or ground via the inductance. The conductance of the PMOS and NMOS transistors are controlled by the PMOS and NMOS transistor enable signals, respectively. The adaptive enable signal generator makes a first dead-time between the PMOS and NMOS transistor enable signals decreasing with increasing load current.

Abstract: A power supply apparatus for supplying an output voltage to a load is provided, which comprises a power output unit, a feedback unit and a control unit. The power output unit adjusts and supplies the output voltage to the load in accordance with at least one driving signal. The feedback unit dynamically detects output condition of the power output unit and outputs the corresponding detection result. The control unit determines a skipping ratio for an internal clock in accordance with the detection result output from the feedback unit, and outputs the internal clock with a part of the pulses being skipped to act as the driving signal.

Abstract: A data storage system including an array of storage devices and a storage controller is provided. The array of storage devices is configured to store information in the form of a plurality of stripes. The storage controller is configured to write a plurality of code words forming each stripe to the array of storage devices. The plurality of code words includes a plurality of data blocks and at least one redundancy block. K sets of parameters, which are generated based on a generator polynomial, are previously provided. The storage controller includes an encoder for generating the redundancy blocks according to the K sets of parameters. Once up to K storage devices in the array of storage devices are failed, the data storage system recovers the failed storage devices based on the K sets of parameters and the other un-failed blocks, wherein K can be larger than two.

Abstract: A power supply apparatus for supplying an output voltage to a load is provided, which comprises a power output unit, a feedback unit and a control unit. The power output unit adjusts and supplies the output voltage to the load in accordance with at least one driving signal. The feedback unit dynamically detects output condition of the power output unit and outputs the corresponding detection result. The control unit determines a skipping ratio for an internal clock in accordance with the detection result output from the feedback unit, and outputs the internal clock with a part of the pulses being skipped to act as the driving signal.

Abstract: A delay line, an analog-to-digital converting device and a load-sensing circuit using the same are provided. The delay line comprises a delay-control terminal, a reset terminal, and n delay cells DCELLx (0<x?n). The delay cells DCELL1˜DCELLn are connected in series to each other. Each of the delay cells DCELLx is coupled to the delay-control terminal and the reset terminal for transmitting the first level stage by stage between the delay cells according to a delay time decided by the delay-control terminal in a sensing period. The outputs of all delay cells are reset to the second level when the sensing period is finished. The sensing period is decided by the signal from the reset terminal. Wherein, at least an output terminal ty (0<y?n) of a delay cell DCELLy among the delay cells DCELL1˜DCELLn used as output terminal of the delay line.

Abstract: A delay line, an analog-to-digital converting device and a load-sensing circuit using the same are provided. The delay line comprises a delay-control terminal, a reset terminal, n delay cells DCELLx (0<x?n). The delay cells DCELL1˜DCELLn are connected in series to each other. Each of the delay cells DCELLx is coupled to the delay-control terminal and the reset terminal for transmitting the first level stage by stage between the delay cells according to a delay time decided by the delay-control terminal in a sensing period. The outputs of all delay cells are reset to the second level when the sensing period is finished. The sensing period is decided by the signal from the reset terminal. Wherein, at least an Output tenninal ty (0<y?n) of a delay cell DCELLy among the delay cells DCELL1˜DCELLn used as output terminal of the delay line.

Abstract: A DC-DC converter includes an error amplifier that includes an operational transconductance amplifier (OTA), a compensation circuit, and a fast transient controller. The OTA includes a compensation resistor, a compensation capacitor of Cz, and a Miller circuit. The equalization capacitance generated by the compensation capacitor and the Miller circuit is (1+k) Cz. The Miller circuit includes three transistors operated in the triode region. The ratio of the current through the transistors is 1:mk:(1?m)k. The current through the compensation capacitor in a second mode is (1+mk) times that in a first mode. The fast transient controller switches the Miller circuit between the first and second modes according to a feedback voltage dependent on the output voltage of the DC-DC converter.