Abstract: A semiconductor device, which comprises a semiconductor substrate, an epitaxial layer, first metal structures, first doped regions, second metal structures, second doped regions, a conductive layer and a Schottky layer. The epitaxial layer is disposed on the semiconductor substrate. The first metal structures are disposed in the epitaxial layer. The first metal structures extend along a first direction and have a first width in a second direction. The first doped regions are disposed in the epitaxial layer and extend from below each first metal structure to the sidewall of each first metal structure. The second metal structure is disposed in the epitaxial layer. The second metal structures extend along the first direction and have a second width in the second direction, wherein the first width is larger than the second width. The conductive layer is disposed under the semiconductor substrate, and the Schottky layer is disposed on the epitaxial layer.

Abstract: A semiconductor device includes a substrate, a gate dielectric layer, a gate electrode, a field plate, a source electrode and a drain electrode. The gate dielectric layer is disposed on the substrate and includes a first portion having a first thickness, a second portion having a second thickness, and a third portion having a third thickness. The first, second and third thicknesses are different from each other, and the first thickness is smaller than the second and third thicknesses. The gate electrode is disposed on the first portion of the gate dielectric layer. The field plate is separated from and electrically coupled to the gate electrode, and is disposed on the second and third portions of the gate dielectric layer. The source and drain electrodes are disposed on the sides of the gate electrode and the field plate, respectively.

Abstract: A semiconductor device includes an epitaxial layer, at least one gate trench, and at least one trench gate structure. The gate trench includes a lower gate trench and an upper gate trench, and a width of the lower gate trench is less than a width of the upper gate trench. The trench gate structure is disposed in the gate trench, and the trench gate structure includes a bottom gate structure, a middle gate structure, and a top gate structure. The thickness of the second gate dielectric layer of the middle gate structure is less than the thickness of the first gate dielectric layer of the bottom gate structure. The thickness of the third gate dielectric layer of the top gate structure is less than the thickness of the second gate dielectric layer of the middle gate structure. The first, second, and third gate electrodes are separated from each other.

Abstract: A semiconductor device, including: a substrate having a first conductive type, an epitaxial layer disposed on the substrate, a doped region disposed in the epitaxial layer, and a gate electrode disposed through the doped region and extending into the epitaxial layer. The epitaxial layer has the first conductive type, and the doped region has a second conductive type different from the first conductive type. The gate electrode includes a first structure having a first dimension, and a second structure above the first structure. The second structure includes a main portion and a protruding portion below the main portion, wherein the main portion has a second dimension larger than the first dimension, and the protruding portion has the first dimension.

Abstract: A semiconductor device includes a substrate, a gate dielectric layer, a gate electrode, a field plate, a source electrode and a drain electrode. The gate dielectric layer is disposed on the substrate and includes a first portion having a first thickness, a second portion having a second thickness, and a third portion having a third thickness. The first, second and third thicknesses are different from each other, and the first thickness is smaller than the second and third thicknesses. The gate electrode is disposed on the first portion of the gate dielectric layer. The field plate is separated from and electrically coupled to the gate electrode, and is disposed on the second and third portions of the gate dielectric layer. The source and drain electrodes are disposed on the sides of the gate electrode and the field plate, respectively.

Abstract: A multi-trench schottky diode includes a semiconductor base layer, a back metal layer, an epitaxial layer, an interlayer dielectric layer, a first metal layer, a passivation layer and a second metal layer. The epitaxial layer on the semiconductor base layer includes a termination trench structure, a first trench structure, a second trench structure and a third trench structure. The dielectric layer is on the epitaxial layer in a termination area. The first metal layer stacked on the termination trench structure and the interlayer dielectric layer extends between the second trench structure and the third trench structure. The passivation layer is on the first metal layer and the interlayer dielectric layer. The second metal layer on the first metal layer and the passivation layer extends to the first trench structure. Thus, the electric field is dispersed and the voltage breakdown can be avoided with the trench structures in the termination area.

Abstract: A Schottky diode with multiple guard ring structures includes a semiconductor base layer, a back metal layer, an epitaxial layer, a dielectric layer, a first metal layer, a passivation layer and a second metal layer. The epitaxial layer on the semiconductor base layer includes a terminal trench structure, a first ion implantation guard ring, a second ion implantation guard ring and a third ion implantation guard ring. The dielectric layer is on the epitaxial layer in a termination area. The first metal layer is on the terminal trench structure and the dielectric layer. The passivation layer is on the first metal layer and the dielectric layer. The second metal layer is on the first metal layer and the passivation layer. Widths of the first, second and third ion implantation guard rings decrease in order, so that the voltage can be distributed step by step.

Abstract: A multi-trench schottky diode includes a semiconductor base layer, a back metal layer, an epitaxial layer, an interlayer dielectric layer, a first metal layer, a passivation layer and a second metal layer. The epitaxial layer on the semiconductor base layer includes a termination trench structure, a first trench structure, a second trench structure and a third trench structure. The dielectric layer is on the epitaxial layer in a termination area. The first metal layer stacked on the termination trench structure and the interlayer dielectric layer extends between the second trench structure and the third trench structure. The passivation layer is on the first metal layer and the interlayer dielectric layer. The second metal layer on the first metal layer and the passivation layer extends to the first trench structure. Thus, the electric field is dispersed and the voltage breakdown can be avoided with the trench structures in the termination area.

Abstract: A Schottky diode with multiple guard ring structures includes a semiconductor base layer, a back metal layer, an epitaxial layer, a dielectric layer, a first metal layer, a passivation layer and a second metal layer. The epitaxial layer on the semiconductor base layer includes a terminal trench structure, a first ion implantation guard ring, a second ion implantation guard ring and a third ion implantation guard ring. The dielectric layer is on the epitaxial layer in a termination area. The first metal layer is on the terminal trench structure and the dielectric layer. The passivation layer is on the first metal layer and the dielectric layer. The second metal layer is on the first metal layer and the passivation layer. Widths of the first, second and third ion implantation guard rings decrease in order, so that the voltage can be distributed step by step.

Abstract: A PIN diode is formed on an insulating structure on a substrate of semiconductor. The insulating structure is disposed on a high voltage doped region in the substrate. The PIN diode includes a semiconductor layer, disposed on the insulating structure. The semiconductor layer includes a first doped region of a first conductivity type, at least one second doped region of a second conductivity type, and at least one intrinsic region without being doped or lightly doped between the first doped region and the at least one second doped region. The first conductive type is opposite to the second conductivity type. At least one interconnection structure is disposed on the insulating structure to electrically connect the at least one intrinsic region to the high voltage doped well.

Abstract: A PIN diode is formed on an insulating structure on a substrate of semiconductor. The insulating structure is disposed on a high voltage doped region in the substrate. The PIN diode includes a semiconductor layer, disposed on the insulating structure. The semiconductor layer includes a first doped region of a first conductivity type, at least one second doped region of a second conductivity type, and at least one intrinsic region without being doped or lightly doped between the first doped region and the at least one second doped region. The first conductive type is opposite to the second conductivity type. At least one interconnection structure is disposed on the insulating structure to electrically connect the at least one intrinsic region to the high voltage doped well.