SEMICONDUCTOR DEVICE AND METHOD FORMING THE SAME
A semiconductor device, including: a substrate having a first conductive type, an epitaxial layer disposed on the substrate, a doped region disposed in the epitaxial layer, and a gate electrode disposed through the doped region and extending into the epitaxial layer. The epitaxial layer has the first conductive type, and the doped region has a second conductive type different from the first conductive type. The gate electrode includes a first structure having a first dimension, and a second structure above the first structure. The second structure includes a main portion and a protruding portion below the main portion, wherein the main portion has a second dimension larger than the first dimension, and the protruding portion has the first dimension.
Latest Vanguard International Semiconductor Corporation Patents:
- SEMICONDUCTOR DEVICE
- MICRO-ELECTRO-MECHANICAL SYSTEM DEVICE AND PIEZOELECTRIC COMPOSITE STACK THEREOF
- Semiconductor structure, high electron mobility transistor and fabrication method thereof
- SEMICONDUCTOR STRUCTURE AND METHODS FOR MANUFACTURING THE SAME
- METHOD OF FABRICATING MICRO-ELECTROMECHANICAL SYSTEM DEVICE
The present disclosure is related to a semiconductor device and method forming the same, and in particular it is related to a “split-gate” design and method forming the same.
Description of the Related ArtA conventional metal-oxide semiconductor field effect transistor (MOSFET) is a popular discrete power device. A particular power device—one with a vertically diffused configuration—has a P-N junction structure composed of an N-type drift region and an overlying P-type doped region. The P-N junction structure is mainly used to withstand the voltage applied to the conventional metal-oxide semiconductor field effect transistor. When improving the operation voltage of a metal-oxide semiconductor field effect transistor, a reduced dopant concentration and a thicker N-type drift region is required. The ways to improve the withstood voltage of the P-N junction structure results in an increased on-resistance (Ron) of the conventional metal-oxide semiconductor field effect transistor. The on-resistance of the conventional metal-oxide semiconductor field effect transistor is limited by the dopant concentration and the thickness of the N-type drift region.
The vertically diffused configuration has the advantage of taking up less space in the circuit. However, due to the vertically diffused configuration, the thickness of the N-type drift region may affect the overall performance of the device. Although 5 increasing the thickness of the N-type drift region can improve the operation voltage and thereby enhance the breakdown voltage, doing so may also increase on-resistance, which leads to higher heat and more power loss. In other words, there is a trade-off between the breakdown voltage and the on-resistance. Therefore, it is necessary to propose innovative ways to address the trade-off issue.
SUMMARYIn an embodiment, a semiconductor device, including: a substrate having a first conductive type, an epitaxial layer disposed on the substrate, a doped region disposed in the epitaxial layer, and a gate electrode disposed through the doped region and extending into the epitaxial layer. The epitaxial layer has the first conductive type, and the doped region has a second conductive type different from the first conductive type. The gate electrode includes a first structure having a first dimension, and a second structure above the first structure. The second structure includes a main portion and a protruding portion below the main portion, wherein the main portion has a second dimension larger than the first dimension, and the protruding portion has the first dimension.
In another embodiment, a method forming a semiconductor device, including: providing a substrate and an epitaxial layer on the substrate; forming a doped region in the epitaxial layer; forming a gate trench penetrating the doped region and extending into the epitaxial layer. The gate trench includes a first opening having a first width, and a second opening below the first opening, wherein the second opening has a second width smaller than the first width. The method further includes filling the second opening with a metal material; etching back the metal material into a first structure of a gate electrode, wherein a top surface of the first structure is lower than a top of the second opening; depositing a gate dielectric layer on the top surface of the first structure, wherein the gate dielectric layer is positioned lower than the top of the second opening; and forming a second structure of the gate electrode on the gate dielectric layer and filling a remaining portion of the second opening and the first opening.
The disclosure can be more fully understood from the following detailed description when read with the accompanying figures. It is worth noting that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, a first feature is formed on a second feature in the description that follows may include embodiments in which the first feature and second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and second feature, so that the first feature and second feature may not be in direct contact.
It should be understood that additional steps may be implemented before, during, or after the illustrated methods, and some steps might be replaced or omitted in other embodiments of the illustrated methods.
Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “on,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to other elements or features as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
In the present disclosure, the terms “about,” “approximately” and “substantially” typically mean±20% of the stated value, more typically ±10% of the stated value, more typically ±5% of the stated value, more typically ±3% of the stated value, more typically ±2% of the stated value, more typically ±1% of the stated value, and even more typically ±0.5% of the stated value. The stated value of the present disclosure is an approximate value. That is, when there is no specific description of the terms “about,” “approximately” and “substantially”, the stated value includes the meaning of “about,” “approximately” or “substantially”.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It should be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined in the embodiments of the present disclosure.
The present disclosure may repeat reference numerals and/or letters in following embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
A power device, such as a metal-oxide semiconductor field effect transistor (MOSFET), may be extensively used in the power system components of analog circuits and digital circuits. In order to reduce the power loss of the power device, on-resistance must be reduced. From previous experiments, it has been discovered that decreasing the Epi thickness may reduce the undesirable on-resistance. However, beyond a certain extent of the Epi thickness reduction, the breakdown voltage of the power device cannot maintain at an acceptable level. Simply stated, increasing the Epi thickness increases both the breakdown voltage and the on-resistance, while decreasing the Epi thickness decreases both the breakdown voltage and the on-resistance. Adjusting only the Epi thickness cannot enhance the breakdown voltage and suppress the on-resistance simultaneously.
It has been discovered that implementing a “split-gate” structure into the metal-oxide semiconductor field effect transistor can maintain the breakdown voltage and reduce the on-resistance. The arrangement of the “split-gate” structure may drive the electric field toward the drain terminal, which in turn increases the breakdown voltage and decreases the on-resistance. The “split-gate” includes two structures of different dimensions. The structure with larger dimension determines the on-resistance, and the structure with smaller dimension determines the breakdown voltage. More specifically, the present disclosure introduces an innovative protruding portion extending from the structure of larger dimension. The protruding portion has the smaller dimension, which allows for the on-resistance to be further suppressed.
Referring to
In other embodiments, the substrate 100 may also be a semiconductor on insulator (SOI) substrate. The semiconductor on insulator substrate may include a base plate, a buried oxide layer disposed on the base plate, and a semiconductor layer disposed on the buried oxide layer. Furthermore, the substrate 100 may be a first conductive type or a second conductive type. In the following embodiments, the first conductive type and the second conductive type may represent an N-type and a P-type, respectively. The first conductive type (N-type) and the second conductive type (P-type) may each be doped with appropriate dopants (or impurities). The N-type dopants may include Arsenic while the P-type dopants may include Boron. In a specific embodiment of the present disclosure, the substrate 100 may be the first conductive type (N-type), with a doping concentration approximately between 1×1019 cm−3 and 3×1019 cm−3.
In other embodiments, the substrate 100 may include isolation structures (not shown) to define active regions and to electrically isolate active region elements within or above the substrate 100, but the present disclosure is not limited thereto. The isolation structures may include deep trench isolation (DTI) structures, shallow trench isolation (STI) structures, or local oxidation of silicon (LOCOS) structures. In some embodiments, the formation of the isolation structures may include, for example, forming an insulating layer on the substrate 100, selectively etching the insulating layer and the substrate 100 to form trenches that extend from the top surface of the substrate 100 to a position within the substrate 100, in which the trenches are located between adjacent active regions. Next, the formation of the isolation structures may include growing rich nitrogen-containing (such as silicon oxynitride) liners along the trenches, followed by filling insulating materials (such as silicon dioxide, silicon nitride, or silicon oxynitride) into the trenches with deposition processes. After that, an annealing process is performed on the insulating materials in the trenches, followed by a planarization process on the substrate 100 to remove excessive insulating materials, so the insulating materials in the trenches are level with the top surface of the substrate 100.
Still referring to
Referring to
Still referring to
Referring to
The first structure 160A and the second structure 160B of the gate electrode 160 are “split” by a portion of the gate dielectric layer 150 (or the second portion 150B), demonstrating the “split-gate” feature of the present disclosure. The first structure 160A has a lateral dimension approximately between 3.5 μm and 4.0 μm, and a vertical dimension approximately between 0.6 μm and 0.8 μm. According to some embodiments of the present disclosure, the second structure 160B of the gate electrode 160 further includes a main portion and a protruding portion extended out from the bottom of the main portion. The main portion of the second structure 160B has a lateral dimension approximately between 0.85 μm and 0.95 μm, and a vertical dimension approximately between 1.2 μm and 1.5 μm. The protruding portion of the second structure 160B has the same lateral dimension as that of the first structure 160A, while the vertical dimension of the protruding portion of the second structure 160B may be approximately between 0.15 μm and 0.25 μm, for example, approximately 0.20 μm.
As shown in
Still referring to
Materials of the gate dielectric layer 150 may include silicon oxide, silicon nitride, or multilayers thereof. In other embodiments, the gate dielectric layer 150 includes materials with a high dielectric constant, and in these embodiments, the gate dielectric layer 150 may have a dielectric constant (or k value) greater than about 7.0, and may include a metal oxide or a silicate of hafnium (Hf), aluminum, zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium, lead (Pb), the like, or combinations thereof. The thickness of the gate dielectric layer 150 may be approximately between 500 Å and 700 Å, for example, approximately 600 Å. According to some embodiments of the present disclosure, the first portion 150A, the second portion 150B, and the third portion 150C may have the same thickness. It should be understood that if the thickness of the gate dielectric layer 150 is too large, excessive capacitance may be generated (especially between the first structure 160A and the second structure 160B). If the thickness of the gate dielectric layer 150 is too small, then the insulation function may be compromised. The gate dielectric layer 150 may be formed by molecular beam deposition (MBD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), the like, or combinations thereof.
As shown in
Referring to
Still referring to
The source electrodes 230 may function as a transistor source terminal of the semiconductor device 10. The materials of the source electrodes 230 may be similar to those of the gate electrode 160, and the details are not described again herein to avoid repetition. The thickness of the source electrodes 230 may be approximately between 0.35 pm and 0.55 μm. The doped contact regions 220 and the source electrodes 230 may be formed by chemical vapor deposition, physical vapor deposition (PVD), atomic layer deposition, the like, or combinations thereof. After forming the doped contact regions 220 and before forming the source electrode 230, the doped contact regions 220 may be doped using the ion implantation and/or the diffusion process.
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
As shown in
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
The lateral distance between the gate electrode 160 and one of the source electrodes 230 may be defined as a mesa width. As shown in
In a specific embodiment, an exemplary device having the “split-gate” feature with the protruding portion is being compared with a conventional device having a single gate electrode of unifying dimension. The design features are listed and the electrical parameters are measured. The relevant data is summarized in Table 1.
In order to make a valid comparison, parameters such as the Epi thickness, the gate trench depth, and the pitch will remain the same between the conventional design and the innovative design. Since the trench of the conventional design has only one single dimension, there can only be one trench width, hence one mesa width. It should be noted that the pitch equals the sum of twice the mesa width and the trench width. For the innovative design, the pitch equals the sum of twice the first mesa width and the trench 1st width (3.25 μm=2×1.15 μm+0.95 μm), or the sum of twice the second mesa width and the trench 2nd width (3.25 μm=2×1.35 μm+0.55 μm).
In this specific embodiment, applying the “split-gate” feature with the protruding portion can increase the breakdown voltage by 20.51%, and decrease the on-resistance by 35.96%. The threshold voltage has dropped by 23.04%, but the shifted value should still be acceptable to the industrial standard. Moreover, because the enhanced operation voltage, the saturated drain current has also been improved.
Even though an extra mask may be needed to fabricate the gate trench 140 of two different dimensions, the resulting device has demonstrated superior electrical performance. In the conventional design, the electric field may be concentrated near the bottom of the gate electrode. The “split-gate” feature of the innovative design may drive the electric field toward the drain terminal to enhance the breakdown voltage. The protruding portion of the gate structure of larger dimension can further suppress the on-resistance. With the features described, the semiconductor device 10 may successfully increase the breakdown voltage and decrease the on-resistance concurrently.
The foregoing outlines features of several embodiments so that those skilled in the art will better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection should be determined through the claims. In addition, although some embodiments of the present disclosure are disclosed above, they are not intended to limit the scope of the present disclosure.
Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that may be realized with the present disclosure should be or are in any single embodiment of the disclosure. Rather, language referring to the features and advantages is understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, discussions of the features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same embodiment.
Furthermore, the described features, advantages, and characteristics of the disclosure may be combined in any suitable manner in one or more embodiments. One skilled in the prior art will recognize, in light of the description herein, that the disclosure can be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the disclosure.
Claims
1. A semiconductor device, comprising:
- a substrate 100 having a first conductive type;
- an epitaxial layer 110 disposed on the substrate 100, wherein the epitaxial layer 110 has the first conductive type;
- a doped region 120 disposed in the epitaxial layer 110, wherein the doped region 120 has a second conductive type different from the first conductive type;
- and
- a gate electrode 160 disposed through the doped region 120 and extending into the epitaxial layer 110, wherein the gate electrode 160 comprising: a first structure 160A having a first dimension; and a second structure 160B above the first structure 160A, wherein the second structure 160B comprises a main portion and a protruding portion below the main portion, wherein the main portion has a second dimension larger than the first dimension, and the protruding portion has the first dimension.
2. The semiconductor device of claim 1, further comprising a gate dielectric layer 150, wherein the gate dielectric layer 150 comprising:
- a first portion 150A disposed on opposite sides and a bottom of the first structure 160A;
- a second portion 150B disposed between the first structure 160A and the protruding portion of the second structure 160B; and
- a third portion 150C disposed on opposite sides of the second structure 160B.
3. The semiconductor device of claim 1, wherein the protruding portion of the second structure 160B is vertically located between the first structure 160A and the main portion of the second structure 160B.
4. The semiconductor device of claim 1, further comprising a well region 130 disposed in the doped region 120, wherein the well region 130 has the first conductive type.
5. The semiconductor device of claim 4, wherein the main portion of the second structure 160B of the gate electrode 160 is disposed through the well region 130 and extends into the doped region 120.
6. The semiconductor device of claim 1, wherein the protruding portion of the second structure 160B of the gate electrode 160 is entirely disposed in the doped region 120.
7. The semiconductor device of claim 1, wherein the first structure 160A of the gate electrode 160 is disposed across the doped region 120 and the epitaxial layer 110.
8. The semiconductor device of claim 1, further comprising an interlayer dielectric (ILD) layer 200 disposed on the epitaxial layer 110 and the gate electrode 160.
9. The semiconductor device of claim 8, further comprising a source electrode 230 disposed through the interlayer dielectric layer 200 and extending into the well region 130.
10. The semiconductor device of claim 9, further comprising a doped contact region 220 below the source electrode 230 and extending into the doped region 120, wherein the doped contact region 220 has a second conductive type.
11. The semiconductor device of claim 1, further comprising a drain electrode 240 disposed on another side of the substrate 100 opposite the epitaxial layer 100.
12. A method forming a semiconductor device, comprising:
- providing a substrate 100 and an epitaxial layer 110 on the substrate 100;
- forming a doped region 120 in the epitaxial layer 110;
- forming a gate trench 140 penetrating the doped region 120 and extending into the epitaxial layer 110, wherein the gate trench 140 comprising: a first opening 140A having a first width W1; and a second opening 140B below the first opening 140A, wherein the second opening 140B has a second width W2 smaller than the first width W1;
- filling the second opening 140B with a metal material;
- etching back the metal material into a first structure 160A of a gate electrode 160, wherein a top surface of the first structure 160A is lower than a top of the second opening 140B;
- depositing a gate dielectric layer 150 on the top surface of the first structure 160A, wherein the gate dielectric layer 150 is positioned lower than the top of the second opening 140B; and
- forming a second structure 160B of the gate electrode 160 on the gate dielectric layer 150 and filling a remaining portion of the second opening 140B and the first opening 140A.
13. The method of claim 12, wherein the gate dielectric layer 150 further extends onto opposite sides and a bottom of the gate electrode 160.
14. The method of claim 12, further comprising forming a well region 130 in the doped region 120.
15. The method of claim 14, wherein the first opening 140A penetrates through the well region 130 and extends into the doped region 120, and the second opening 140B is formed across the doped region 120 and the epitaxial layer 110.
16. The method of claim 12, wherein a first depth D1 of the first opening 140A is smaller than a second depth D2 of the second opening 140B.
17. The method of claim 12, further comprising:
- depositing an interlayer dielectric layer 200 on the epitaxial layer 110 and the gate electrode 160;
- forming a source trench 210 penetrating the interlayer dielectric layer 200 and extending into the doped region 120; and
- filling the source trench 210 with a source electrode 230.
18. The method of claim 17, further comprising forming a doped contact region 220 in the source trench 210 before filling the source electrode 230, wherein the doped contact region 220 is in direct contact with the doped region 120.
19. The method of claim 17, wherein a first mesa width M1 between the second structure 160B and the source electrode 230 is smaller than a second mesa width M2 between the first structure 160A and the source electrode 230.
20. The method of claim 12, further comprising forming a drain electrode 240 on another side of the substrate 100 opposite the epitaxial layer 100.
Type: Application
Filed: Dec 23, 2021
Publication Date: Jun 29, 2023
Applicant: Vanguard International Semiconductor Corporation (Hsinchu)
Inventors: Syed-Sarwar IMAM (Hsinchu City), Chia-Hao LEE (Jhubei City)
Application Number: 17/561,317