Abstract: The invention relates to a microelectronic device comprising a transistor (T1, T2) comprising at least two channels (41a, 41b, 41c) stacked along a main direction (z),. a first gate (G1) partially surrounding one of the channels (41a, 41b, 41c), a second gate (G2) partially surrounding said channel (41), a source (42) and a drain (43) either side of the channels (41a, 41b, 41c), and source and drain contacts (60S, 60, 60D) connected respectively to the source (42) and to the drain (43), a gate dielectric layer (70, 71, 72) separating each channel (41) of the gates-all-around (G1, G2). The first and second gates (G1, G2) are isolated from one another, such that they can be independently biased. The invention also relates to a method for producing such a device.

Abstract: The invention relates to a device comprising transistors (T1, T2, T3), each comprising: a channel (41) with the basis of a semiconductive material, a gate-all-around (50), totally surrounding said channel (41), a source (42) and a drain (43) on either side of the channel (41), and source and drain contacts (60S, 60, 60D), a gate dielectric layer (30) separating the channel (41) and the gate-all-around (50), spacers (70) on either side of the gate (50). Advantageously, the gate dielectric layer (30) and the spacers (70) are formed by at least one single and same continuous layer (73) surrounding the gate-all-around (50). The invention also relates to a method for producing such a device.

Abstract: The invention relates to a device comprising a transistor (T1, T2) comprising: a source (42) and a drain (43), a plurality of channels (41a, 41b, 41c) based on a semi-metallic material, a gate-all-around (50) surrounding the channels (41a, 41b, 41c), a gate dielectric layer (30) separating each channel (41a, 41b, 41c) and the gate-all-around (50), source and drain contacts (40S, 40D) based on the semi-metallic material, Advantageously, the gate-all-around (50) totally surrounds one or more of the channels (41a, 41b, 41c), according to a GAA architecture. The invention also relates to a method for producing such a device.

Abstract: A method for producing a device comprising GAA transistors. Advantageously, the channels of the transistors are produced by deposition of a semiconductor material, preferably a 2D material, after successive removal of certain layers of the initial stack. The gates-all-around are produced after selective removal of the other layers from the initial stack. The initial stack does not comprise the semiconductor material, nor the material of the gates. The subsequent deposition of the semiconductor material aims to better preserve the semiconductor material.

Abstract: An in-memory computing circuit includes a plurality of memory planes. Each plane forming a two-dimensional matrix of non-volatile, resistive and programmable memory cells. Each memory cell having a selection node, a first input/output node and a second input/output node. The computing circuit comprising at least one elementary group of memory cells comprising: a first memory cell belonging to any one of the memory planes and intended to store a first input datum; a second memory cell belonging to any one of the memory planes and intended to store a second input datum; a third memory cell belonging to a memory plane different from that of the first and of the second memory cell. The third memory cell being intended to store the result of a first logic operation with the first and second input data as operands.

Abstract: A device with stacked transistors includes a first transistor of a first type, in particular N or P, the first transistor having a channel formed in one or more first semi-conducting rods of a semi-conducting structure including semi-conducting rods disposed above each other and aligned with each other, and a second transistor of a second type, in particular P or N, with a gate-surrounding gate and a channel region formed in one or more second semi-conducting rods of said semi-conducting structure and disposed above the first semi-conducting rods. The source block of the second transistor is distinct from the source and drain block of the second transistor, and the drain block of the second transistor is distinct from the drain and source blocks of the second transistor.

Abstract: A FET microelectronic device comprising: a semiconductor layer a first area of which forms a channel; a gate and a gate dielectric layer or a ferroelectric memory layer, arranged against the first area; dielectric spacers arranged against sidewalls of the gate; source/drain regions electrically coupled to the first area via second areas of the active layer extending between the source/drain regions and the dielectric spacers; wherein the second areas form a continuous layer with the first area, and the first area forms a semiconductor portion such that the gate covers several distinct faces of the semiconductor portion.

Abstract: A microelectronic device comprising: a semiconductor layer (120) several first areas (122) of which are superposed and form a channel; an electrostatic control gate (110) and a gate dielectric layer (112) or a ferroelectric memory layer (112) parts of which are each arranged between a part (106, 108) of the gate and one amongst the first areas; dielectric spacers (114) arranged against sidewalls of the gate; source (116)/drain (118) regions electrically coupled to the first areas by second areas (124) of the semiconductor layer extending between the source/drain regions and the spacers, and/or between a substrate (102) and each of the source/drain regions; and wherein the second areas are not arranged directly against the layer and form a continuous layer with the first areas.

Abstract: A memory device (100) comprising at least one memory stack (158) electrically connected in series with a selection transistor, comprising: a semiconductor layer (120) first areas (122) of which are superimposed and form a channel; an electrostatic control gate (110) and a gate dielectric layer (112) such that parts of the gate dielectric layer are each arranged between a part (106, 108) of the gate and one of the first areas; dielectric spacers (114) arranged against sidewalls of the gate; contact regions (116, 118) electrically coupled to the first areas via second areas (124) of the semiconductor layer extending between the contact regions and the spacers, one of the contact regions (118) comprising the memory stack; and wherein the second areas form a continuous layer with the first areas.

Abstract: Stack of layers of monocrystalline materials suitable for producing microelectronic devices with 3D architecture comprising transistors, including several first layers of monocrystalline material, several second layers of monocrystalline material different from that of the first layers, and at least one third layer of monocrystalline material different from those of the first and second layers, wherein: a first of the monocrystalline materials of the first, second and third layers corresponds to intrinsic silicon; a second of the monocrystalline materials of the first, second and third layers corresponds to intrinsic SiGe; a third of the monocrystalline materials of the first, second and third layers corresponds to p-doped silicon or p-doped SiGe.

Abstract: A microelectronic device includes a first transistor having a first drain and a first source, a first doped zone constituting one from among the first drain and the first source, a second doped zone constituting the other from among the first drain and the first source, a second transistor comprising a second drain and a second source, a third doped zone constituting the second source or the second drain, a fourth doped zone constituting the other from among the second drain and the second source, a dielectric layer having an upper face in contact with the four doped zones and a rear gate in contact with a lower face of the dielectric layer. The second doped zone and the fourth doped zone form a common electrode.

Abstract: A device includes gate-all-around transistors and method for manufacturing such a device. A method for manufacturing a microelectronic device includes at least two transistors each comprising a channel in the shape of a wire extending in a first direction x, a gate surrounding said channel, a source and a drain, said transistors being stacked in a third direction z and each occupying a level nz (z=1 . . . 4) of given altitude in the third direction z.

Abstract: A microelectronic device includes a field-effect n-MOS transistor, a first N-doped zone, constituting one from among the drain and the source of the n-MOS transistor and a second N-doped zone, constituting the other from among the drain and the source of the n-MOS transistor. The device further includes a field-effect p-MOS transistor, a first P-doped zone, constituting one from among the drain and the source of the p-MOS transistor, a dielectric layer in contact with the doped zones and a rear gate. The n-MOS transistor and the p-MOS transistor are separated by a PN junction.

Abstract: An in-memory computing circuit includes a plurality of memory planes. Each plane forming a two-dimensional matrix of non-volatile, resistive and programmable memory cells. Each memory cell having a selection node, a first input/output node and a second input/output node. The computing circuit comprising at least one elementary group of memory cells comprising: a first memory cell belonging to any one of the memory planes and intended to store a first input datum; a second memory cell belonging to any one of the memory planes and intended to store a second input datum; a third memory cell belonging to a memory plane different from that of the first and of the second memory cell. The third memory cell being intended to store the result of a first logic operation with the first and second input data as operands.

Abstract: A memory structured in lines and columns over several superimposed levels, each level comprising an array of memory elements and gate-all-around access transistors, each transistor including a semiconductor nanowire and each gate being insulated from the gates of the other levels, further comprising: conductive portions, each crossing at least two levels and coupled to first ends of the nanowires of one column of the levels; memory stacks, each crossing the levels and coupled to second ends of the nanowires of said column; first conductive lines, each connected to the conductive portions of the same column; word lines each extending in the same level while coupling together the gates of the same line and located in said level.

Abstract: The invention provides a microelectronic device comprising at least two memory cells each comprising a so-called selection transistor and a memory element associated with said selection transistor, each transistor comprising a channel in the form of a wire extending in a first direction (x), a gate bordering said channel, a source extending in a second direction (y), and a drain connected to the memory element, said transistors being stacked in a third direction (z) and each occupying a given altitude level in the third direction (z), the microelectronic device wherein the source and the drain are entirely covered by spacers projecting in the third direction (z) in a plane (xy). The invention also provides a method for manufacturing such a device.

Abstract: A method for manufacturing a pFET transistor, the method for manufacturing the transistor including providing a base structure comprising a silicon channel and a gate structure, the gate structure surrounding the channel leaving two flanks of the channel free; growing a first layer made from silicon-germanium alloy on the flanks of the channel; enriching the channel with germanium atoms from the first layer; and forming a drain region and a source region on either side of the channel.

Abstract: A process for fabricating an electronic component incorporating double quantum dots and split gates includes providing a substrate surmounted with a stack of a semiconductor layer and of a dielectric layer that is formed above the semiconductor layer. The process also includes forming a mask on the dielectric layer and etching the dielectric layer and the semiconductor layer with the pattern of the mask, so as to form a stack of a semiconductor nanowire and of a dielectric hard mask. Finally, the process includes depositing a gate material on all of the wafer and carrying out a planarization, until the dielectric hard mask is reached, so as to form first and second gates that are electrically insulated from each other on either side of said nanowire.

Abstract: A method for producing an FET transistor includes producing a transistor channel, comprising at least one semiconductor nanowire arranged on a substrate and comprising first and second opposite side faces; producing at least two dummy gates, each arranged against one of the first and second side faces of the channel; etching a first of the two dummy gates, forming a first gate location against the first side face of the channel; producing a first gate in the first gate location and against the first side face of the channel; etching a second of the two dummy gates, forming a second gate location against the second side face of the channel; and producing a second gate in the second gate location and against the second side face of the channel.

Abstract: Implementation of a device with stacked transistors comprising: a first transistor of a first type, in particular N or P, the first transistor having a channel formed in one or more first semi-conducting rods of a semi-conducting structure including semi-conducting rods disposed above each other and aligned with each other, a second transistor of a second type, in particular P or N, with a gate-surrounding gate and a channel region formed in one or more second semi-conducting rods of said semi-conducting structure and disposed above the first semi-conducting rods, the source block of the second transistor being distinct from the source and drain block of the second transistor, the drain block of the second transistor being distinct from the drain and source blocks of the second transistor.