Patents by Inventor SYLVAIN BARRAUD

SYLVAIN BARRAUD has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10903349
    Abstract: An electronic component with multiple quantum islands is provided, including a substrate on which rests a nanowire made of semiconductor material not intentionally doped; two main control gates resting on the nanowire so as to form respective qubits in the nanowire, the two main control gates being separated by a groove, and bottom and lateral faces of the groove are covered by a dielectric layer; an element made of conductive material formed on the dielectric layer in the groove; a carrier reservoir that is offset with respect to the nanowire, the element made of the conductive material being separated from the carrier reservoir by another dielectric layer such that the element made of the conductive material is coupled to the carrier reservoir by field effect. A method of fabricating an electronic component with multiple quantum islands is also provided.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: January 26, 2021
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Louis Hutin, Sylvain Barraud, Benoit Bertrand, Maud Vinet
  • Publication number: 20200343435
    Abstract: A process for fabricating an electronic component incorporating double quantum dots and split gates includes providing a substrate surmounted with a stack of a semiconductor layer and of a dielectric layer that is formed above the semiconductor layer. The process also includes forming a mask on the dielectric layer and etching the dielectric layer and the semiconductor layer with the pattern of the mask, so as to form a stack of a semiconductor nanowire and of a dielectric hard mask. Finally, the process includes depositing a gate material on all the wafer and carrying out a planarization, until the dielectric hard mask is reached, so as to form first and second gates that are electrically insulated from each other on either side of said nanowire.
    Type: Application
    Filed: October 17, 2018
    Publication date: October 29, 2020
    Applicant: COMMISSARIAT A L' ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sylvain BARRAUD, Louis HUTIN, Maud VINET
  • Publication number: 20200203341
    Abstract: Implementation of a device with stacked transistors comprising: a first transistor of a first type, in particular N or P, the first transistor having a channel formed in one or more first semi-conducting rods of a semi-conducting structure including semi-conducting rods disposed above each other and aligned with each other, a second transistor of a second type, in particular P or N, with a gate-surrounding gate and a channel region formed in one or more second semi-conducting rods of said semi-conducting structure and disposed above the first semi-conducting rods, the source block of the second transistor being distinct from the source and drain block of the second transistor, the drain block of the second transistor being distinct from the drain and source blocks of the second transistor.
    Type: Application
    Filed: December 20, 2019
    Publication date: June 25, 2020
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sylvain Barraud, Jean-Pierre Colinge, Bernard Previtali
  • Publication number: 20200176613
    Abstract: Method for producing an FET transistor, comprising: producing a transistor channel, comprising at least one semiconductor nanowire arranged on a substrate and comprising first and second opposite side faces; producing at least two dummy gates, each arranged against one of the first and second side faces of the channel; etching a first of the two dummy gates, forming a first gate location against the first side face of the channel; producing a first gate in the first gate location and against the first side face of the channel; etching a second of the two dummy gates, forming a second gate location against the second side face of the channel; producing a second gate in the second gate location and against the second side face of the channel.
    Type: Application
    Filed: November 27, 2019
    Publication date: June 4, 2020
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Sylvain BARRAUD, Joris LACORD
  • Patent number: 10522669
    Abstract: A method of making a quantum device with a quantum island structure is provided. The method includes the formation of a stack including a first semiconducting layer based on an undoped semiconducting material on which at least one second doped semiconducting layer is grown by epitaxy, the doping being made during epitaxial growth, a first region belonging to the first semiconducting layer and a second region belonging to the second semiconducting layer being suitable for forming a quantum island.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: December 31, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Sylvain Barraud
  • Publication number: 20190371908
    Abstract: A method of fabricating an electronic component with multiple quantum islands is provided, including supplying a substrate on which rests a nanowire made of semiconductor material not intentionally doped, the nanowire having at least two main control gates resting thereon so as to form respective qubits in the nanowire under the two main control gates, the two main control gates being separated by a groove, top and lateral faces of the two main control gates and a bottom of the groove being covered by a dielectric layer; depositing a conductive material in the groove and on the top of the two main control gates; and planarizing down to the dielectric layer on the top of the two main control gates, so as to obtain an element made of conductive material self-aligned between the main control gates.
    Type: Application
    Filed: May 16, 2019
    Publication date: December 5, 2019
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Louis HUTIN, Sylvain BARRAUD, Benoit BERTRAND, Maud VINET
  • Publication number: 20190371926
    Abstract: An electronic component with multiple quantum islands is provided, including a substrate on which rests a nanowire made of semiconductor material not intentionally doped; two main control gates resting on the nanowire so as to form respective qubits in the nanowire, the two main control gates being separated by a groove, and bottom and lateral faces of the groove are covered by a dielectric layer; an element made of conductive material formed on the dielectric layer in the groove; a carrier reservoir that is offset with respect to the nanowire, the element made of the conductive material being separated from the carrier reservoir by another dielectric layer such that the element made of the conductive material is coupled to the carrier reservoir by field effect. A method of fabricating an electronic component with multiple quantum islands is also provided.
    Type: Application
    Filed: May 16, 2019
    Publication date: December 5, 2019
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Louis HUTIN, Sylvain BARRAUD, Benoit BERTRAND, Maud VINET
  • Publication number: 20190148367
    Abstract: Production of an integrated circuit provided with several superposed levels of transistors, comprising: providing a structure provided with transistors of a lower level covered by an insulating layer itself covered by a stack with a first doped semi-conducting layer according to a doping of a first type, and a second doped semi-conducting layer according to a doping of opposite type, the first doped semi-conducting layer and the second doped semi-conducting layer being superposed and in contact with one another, etching the stack so as to form, on the insulating layer, a first block and a second block, then, removing in a given zone of the second block, the second given doped semi-conducting layer, forming a first gate on the second doped semi-conducting layer of the first block and a second gate on the first doped semi-conducting layer of the second block.
    Type: Application
    Filed: November 8, 2018
    Publication date: May 16, 2019
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Pierre Colinge, Sylvain Barraud, Perrine Batude
  • Patent number: 10217849
    Abstract: Method for making a semiconductor device, comprising: a) making of a stack of crystalline semiconductor layers comprising a first layer and a second layer capable of being selectively etched in relation to the first layer, b) etching of part of the stack, a portion of the first layer forms a nanowire (132) arranged on the second layer, c) selective etching of second layer, d) making, beneath the nanowire, of a sacrificial portion which has an etching selectivity which is greater than that of the second layer, e) making of a sacrificial gate and of an external spacer surrounding the sacrificial gate, f) etching of the stack, revealing ends of the nanowire and of the sacrificial portion aligned with the external spacer, g) selective etching of parts of the sacrificial portion, from its ends, forming aligned cavities beneath the external spacer, h) making of an internal spacer within the cavities.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: February 26, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sylvain Barraud, Emmanuel Augendre, Remi Coquand, Shay Reboh
  • Publication number: 20180175163
    Abstract: Method for making a semiconductor device, comprising: a) making of a stack of crystalline semiconductor layers comprising a first layer and a second layer capable of being selectively etched in relation to the first layer, b) etching of part of the stack, a portion of the first layer forms a nanowire (132) arranged on the second layer, c) selective etching of second layer, d) making, beneath the nanowire, of a sacrificial portion which has an etching selectivity which is greater than that of the second layer, e) making of a sacrificial gate and of an external spacer surrounding the sacrificial gate, f) etching of the stack, revealing ends of the nanowire and of the sacrificial portion aligned with the external spacer, g) selective etching of parts of the sacrificial portion, from its ends, forming aligned cavities beneath the external spacer, h) making of an internal spacer within the cavities.
    Type: Application
    Filed: December 11, 2017
    Publication date: June 21, 2018
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sylvain BARRAUD, Emmanuel Augendre, Remi Coquand, Shay Reboh
  • Publication number: 20180097095
    Abstract: Method of making a quantum device with a quantum island structure, comprising the formation of a stack comprising a first semiconducting layer based on an undoped semiconducting material on which at least one second doped semiconducting layer is grown by epitaxy, the doping being made during epitaxial growth, a first region (212a) belonging to the first semiconducting layer and a second region (214a) belonging to the second semiconducting layer being suitable for forming a quantum island.
    Type: Application
    Filed: October 4, 2017
    Publication date: April 5, 2018
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Sylvain BARRAUD
  • Patent number: 9911841
    Abstract: Single-electron transistor comprising at least: first semiconductor portions forming source and drain regions, a second semiconductor portion forming at least one quantum island, third semiconductor portions forming tunnel junctions between the second semiconductor portion and the first semiconductor portions, a gate and a gate dielectric located on at least the second semiconductor portion, in which a thickness of each of the first semiconductor portions is greater than the thickness of the second semiconductor portion, and in which a thickness of the second semiconductor portion is greater than the thickness of each of the third semiconductor portions.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: March 6, 2018
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Sylvain Barraud, Ivan Duchemin, Louis Hutin, Yann-Michel Niquet, Maud Vinet
  • Patent number: 9876121
    Abstract: A method for making a transistor in which: a) on a substrate, at least one semi-conductor structure is made, which is formed by a stack comprising alternating layer(s) based on at least one first semi-conductor material and layer(s) based on at least one second semi-conductor material different from the first semi-conductor material, b) a zone of the structure is made amorphous using implantations, the zone made amorphous comprising one or more portions of one or more layers based on the second semi-conductor material, c) the portions are removed by selectively etching a second semi-conductor material made amorphous towards the first semi-conductor material (FIG. 2L).
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: January 23, 2018
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Sylvain Barraud, Shay Reboh, Maud Vinet
  • Patent number: 9853124
    Abstract: Method of making a transistor with semiconducting nanowires, including: making a semiconducting nanowire on a support, one portion of the nanowire being covered by a dummy gate, in which the dummy gate and the nanowire are surrounded by a dielectric layer, removing the dummy gate, forming a first space surrounded by first parts of the dielectric layer, making an ion implantation in a second part of the dielectric layer under said first portion, said first parts protecting third parts of the dielectric layer, etching said second part, forming a second space, making a gate in the spaces, and a dielectric portion on the gate and said first parts, making an ion implantation in fourth parts of the dielectric layer surrounding second portions of the nanowire, the dielectric portion protecting said first and third parts, etch said fourth parts.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: December 26, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sylvain Barraud, Emmanuel Augendre, Sylvain Maitrejean, Nicolas Posseme
  • Patent number: 9728405
    Abstract: A semiconductor device is provided, including two semiconductor nanowires superimposed one on top of the other or arranged next to one another, spaced one from the other and forming channel regions of the semiconductor device, a dielectric structure entirely filling a space between the nanowires and which is in contact with the nanowires, a gate dielectric and a gate covering a first of the nanowires, sidewalls of the nanowires and sidewalls of the dielectric structure when the nanowires are superimposed one on top of the other, or covering a part of the upper faces of the nanowires and a part of an upper face of the dielectric structure when the nanowires are arranged next to one another, and wherein the dielectric structure comprises a portion of dielectric material with a relative permittivity greater than or equal to 20.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: August 8, 2017
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Sylvain Barraud, Pierrette Rivallin, Pascal Scheiblin
  • Publication number: 20170141212
    Abstract: Method of making a transistor with semiconducting nanowires, including: making a semiconducting nanowire on a support, one portion of the nanowire being covered by a dummy gate, in which the dummy gate and the nanowire are surrounded by a dielectric layer, removing the dummy gate, forming a first space surrounded by first parts of the dielectric layer, making an ion implantation in a second part of the dielectric layer under said first portion, said first parts protecting third parts of the dielectric layer, etching said second part, forming a second space, making a gate in the spaces, and a dielectric portion on the gate and said first parts, making an ion implantation in fourth parts of the dielectric layer surrounding second portions of the nanowire, the dielectric portion protecting said first and third parts, etch said fourth parts.
    Type: Application
    Filed: November 15, 2016
    Publication date: May 18, 2017
    Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives
    Inventors: Sylvain BARRAUD, Emmanuel Augendre, Sylvain Maitrejean, Nicolas Posseme
  • Publication number: 20160276494
    Abstract: A method for making a transistor in which: a) on a substrate, at least one semi-conductor structure is made, which is formed by a stack comprising alternating layer(s) based on at least one first semi-conductor material and layer(s) based on at least one second semi-conductor material different from the first semi-conductor material, b) a zone of the structure is made amorphous using implantations, the zone made amorphous comprising one or more portions of one or more layers based on the second semi-conductor material, c) the portions are removed by selectively etching a second semi-conductor material made amorphous towards the first semi-conductor material (FIG. 2L).
    Type: Application
    Filed: March 15, 2016
    Publication date: September 22, 2016
    Applicant: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Sylvain BARRAUD, Shay REBOH, Maud VINET
  • Publication number: 20160268406
    Abstract: Single-electron transistor comprising at least: first semiconductor portions forming source and drain regions, a second semiconductor portion forming at least one quantum island, third semiconductor portions forming tunnel junctions between the second semiconductor portion and the first semiconductor portions, a gate and a gate dielectric located on at least the second semiconductor portion, in which a thickness of each of the first semiconductor portions is greater than the thickness of the second semiconductor portion, and in which a thickness of the second semiconductor portion is greater than the thickness of each of the third semiconductor portions.
    Type: Application
    Filed: March 10, 2016
    Publication date: September 15, 2016
    Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives
    Inventors: Sylvain BARRAUD, Ivan DUCHEMIN, Louis HUTIN, Yann-Michel NIQUET, Maud VINET
  • Patent number: 9425255
    Abstract: Fabrication of a microelectronic device on a semiconductor on insulator type substrate, the device being provided with a transistor of a given type, the channel structure of which is formed from semiconducting bar(s), a dielectric area different from the insulating layer of the substrate being provided to replace the insulating layer, facing the transistor channel structure, specifically for this given type of transistor.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: August 23, 2016
    Assignees: Commissariat a l'energie atomique et aux energies alternatives, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Sylvain Barraud, Yves Morand
  • Publication number: 20160133700
    Abstract: Fabrication of a microelectronic device on a semiconductor on insulator type substrate, the device being provided with a transistor of a given type, the channel structure of which is formed from semiconducting bar(s), a dielectric area different from the insulating layer of the substrate being provided to replace the insulating layer, facing the transistor channel structure, specifically for this given type of transistor.
    Type: Application
    Filed: December 29, 2015
    Publication date: May 12, 2016
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Sylvain BARRAUD, Yves MORAND