Patents by Inventor SYLVAIN BARRAUD
SYLVAIN BARRAUD has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10522669Abstract: A method of making a quantum device with a quantum island structure is provided. The method includes the formation of a stack including a first semiconducting layer based on an undoped semiconducting material on which at least one second doped semiconducting layer is grown by epitaxy, the doping being made during epitaxial growth, a first region belonging to the first semiconducting layer and a second region belonging to the second semiconducting layer being suitable for forming a quantum island.Type: GrantFiled: October 4, 2017Date of Patent: December 31, 2019Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventor: Sylvain Barraud
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Publication number: 20190371926Abstract: An electronic component with multiple quantum islands is provided, including a substrate on which rests a nanowire made of semiconductor material not intentionally doped; two main control gates resting on the nanowire so as to form respective qubits in the nanowire, the two main control gates being separated by a groove, and bottom and lateral faces of the groove are covered by a dielectric layer; an element made of conductive material formed on the dielectric layer in the groove; a carrier reservoir that is offset with respect to the nanowire, the element made of the conductive material being separated from the carrier reservoir by another dielectric layer such that the element made of the conductive material is coupled to the carrier reservoir by field effect. A method of fabricating an electronic component with multiple quantum islands is also provided.Type: ApplicationFiled: May 16, 2019Publication date: December 5, 2019Applicant: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Louis HUTIN, Sylvain BARRAUD, Benoit BERTRAND, Maud VINET
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Publication number: 20190371908Abstract: A method of fabricating an electronic component with multiple quantum islands is provided, including supplying a substrate on which rests a nanowire made of semiconductor material not intentionally doped, the nanowire having at least two main control gates resting thereon so as to form respective qubits in the nanowire under the two main control gates, the two main control gates being separated by a groove, top and lateral faces of the two main control gates and a bottom of the groove being covered by a dielectric layer; depositing a conductive material in the groove and on the top of the two main control gates; and planarizing down to the dielectric layer on the top of the two main control gates, so as to obtain an element made of conductive material self-aligned between the main control gates.Type: ApplicationFiled: May 16, 2019Publication date: December 5, 2019Applicant: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Louis HUTIN, Sylvain BARRAUD, Benoit BERTRAND, Maud VINET
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Publication number: 20190148367Abstract: Production of an integrated circuit provided with several superposed levels of transistors, comprising: providing a structure provided with transistors of a lower level covered by an insulating layer itself covered by a stack with a first doped semi-conducting layer according to a doping of a first type, and a second doped semi-conducting layer according to a doping of opposite type, the first doped semi-conducting layer and the second doped semi-conducting layer being superposed and in contact with one another, etching the stack so as to form, on the insulating layer, a first block and a second block, then, removing in a given zone of the second block, the second given doped semi-conducting layer, forming a first gate on the second doped semi-conducting layer of the first block and a second gate on the first doped semi-conducting layer of the second block.Type: ApplicationFiled: November 8, 2018Publication date: May 16, 2019Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Jean-Pierre Colinge, Sylvain Barraud, Perrine Batude
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Patent number: 10217849Abstract: Method for making a semiconductor device, comprising: a) making of a stack of crystalline semiconductor layers comprising a first layer and a second layer capable of being selectively etched in relation to the first layer, b) etching of part of the stack, a portion of the first layer forms a nanowire (132) arranged on the second layer, c) selective etching of second layer, d) making, beneath the nanowire, of a sacrificial portion which has an etching selectivity which is greater than that of the second layer, e) making of a sacrificial gate and of an external spacer surrounding the sacrificial gate, f) etching of the stack, revealing ends of the nanowire and of the sacrificial portion aligned with the external spacer, g) selective etching of parts of the sacrificial portion, from its ends, forming aligned cavities beneath the external spacer, h) making of an internal spacer within the cavities.Type: GrantFiled: December 11, 2017Date of Patent: February 26, 2019Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Sylvain Barraud, Emmanuel Augendre, Remi Coquand, Shay Reboh
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Publication number: 20180175163Abstract: Method for making a semiconductor device, comprising: a) making of a stack of crystalline semiconductor layers comprising a first layer and a second layer capable of being selectively etched in relation to the first layer, b) etching of part of the stack, a portion of the first layer forms a nanowire (132) arranged on the second layer, c) selective etching of second layer, d) making, beneath the nanowire, of a sacrificial portion which has an etching selectivity which is greater than that of the second layer, e) making of a sacrificial gate and of an external spacer surrounding the sacrificial gate, f) etching of the stack, revealing ends of the nanowire and of the sacrificial portion aligned with the external spacer, g) selective etching of parts of the sacrificial portion, from its ends, forming aligned cavities beneath the external spacer, h) making of an internal spacer within the cavities.Type: ApplicationFiled: December 11, 2017Publication date: June 21, 2018Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Sylvain BARRAUD, Emmanuel Augendre, Remi Coquand, Shay Reboh
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Publication number: 20180097095Abstract: Method of making a quantum device with a quantum island structure, comprising the formation of a stack comprising a first semiconducting layer based on an undoped semiconducting material on which at least one second doped semiconducting layer is grown by epitaxy, the doping being made during epitaxial growth, a first region (212a) belonging to the first semiconducting layer and a second region (214a) belonging to the second semiconducting layer being suitable for forming a quantum island.Type: ApplicationFiled: October 4, 2017Publication date: April 5, 2018Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventor: Sylvain BARRAUD
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Patent number: 9911841Abstract: Single-electron transistor comprising at least: first semiconductor portions forming source and drain regions, a second semiconductor portion forming at least one quantum island, third semiconductor portions forming tunnel junctions between the second semiconductor portion and the first semiconductor portions, a gate and a gate dielectric located on at least the second semiconductor portion, in which a thickness of each of the first semiconductor portions is greater than the thickness of the second semiconductor portion, and in which a thickness of the second semiconductor portion is greater than the thickness of each of the third semiconductor portions.Type: GrantFiled: March 10, 2016Date of Patent: March 6, 2018Assignee: Commissariat à l'énergie atomique et aux énergies alternativesInventors: Sylvain Barraud, Ivan Duchemin, Louis Hutin, Yann-Michel Niquet, Maud Vinet
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Patent number: 9876121Abstract: A method for making a transistor in which: a) on a substrate, at least one semi-conductor structure is made, which is formed by a stack comprising alternating layer(s) based on at least one first semi-conductor material and layer(s) based on at least one second semi-conductor material different from the first semi-conductor material, b) a zone of the structure is made amorphous using implantations, the zone made amorphous comprising one or more portions of one or more layers based on the second semi-conductor material, c) the portions are removed by selectively etching a second semi-conductor material made amorphous towards the first semi-conductor material (FIG. 2L).Type: GrantFiled: March 15, 2016Date of Patent: January 23, 2018Assignee: Commissariat a l'energie atomique et aux energies alternativesInventors: Sylvain Barraud, Shay Reboh, Maud Vinet
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Patent number: 9853124Abstract: Method of making a transistor with semiconducting nanowires, including: making a semiconducting nanowire on a support, one portion of the nanowire being covered by a dummy gate, in which the dummy gate and the nanowire are surrounded by a dielectric layer, removing the dummy gate, forming a first space surrounded by first parts of the dielectric layer, making an ion implantation in a second part of the dielectric layer under said first portion, said first parts protecting third parts of the dielectric layer, etching said second part, forming a second space, making a gate in the spaces, and a dielectric portion on the gate and said first parts, making an ion implantation in fourth parts of the dielectric layer surrounding second portions of the nanowire, the dielectric portion protecting said first and third parts, etch said fourth parts.Type: GrantFiled: November 15, 2016Date of Patent: December 26, 2017Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Sylvain Barraud, Emmanuel Augendre, Sylvain Maitrejean, Nicolas Posseme
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Patent number: 9728405Abstract: A semiconductor device is provided, including two semiconductor nanowires superimposed one on top of the other or arranged next to one another, spaced one from the other and forming channel regions of the semiconductor device, a dielectric structure entirely filling a space between the nanowires and which is in contact with the nanowires, a gate dielectric and a gate covering a first of the nanowires, sidewalls of the nanowires and sidewalls of the dielectric structure when the nanowires are superimposed one on top of the other, or covering a part of the upper faces of the nanowires and a part of an upper face of the dielectric structure when the nanowires are arranged next to one another, and wherein the dielectric structure comprises a portion of dielectric material with a relative permittivity greater than or equal to 20.Type: GrantFiled: December 23, 2014Date of Patent: August 8, 2017Assignee: Commissariat à l'énergie atomique et aux énergies alternativesInventors: Sylvain Barraud, Pierrette Rivallin, Pascal Scheiblin
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Publication number: 20170141212Abstract: Method of making a transistor with semiconducting nanowires, including: making a semiconducting nanowire on a support, one portion of the nanowire being covered by a dummy gate, in which the dummy gate and the nanowire are surrounded by a dielectric layer, removing the dummy gate, forming a first space surrounded by first parts of the dielectric layer, making an ion implantation in a second part of the dielectric layer under said first portion, said first parts protecting third parts of the dielectric layer, etching said second part, forming a second space, making a gate in the spaces, and a dielectric portion on the gate and said first parts, making an ion implantation in fourth parts of the dielectric layer surrounding second portions of the nanowire, the dielectric portion protecting said first and third parts, etch said fourth parts.Type: ApplicationFiled: November 15, 2016Publication date: May 18, 2017Applicant: Commissariat a L'Energie Atomique et aux Energies AlternativesInventors: Sylvain BARRAUD, Emmanuel Augendre, Sylvain Maitrejean, Nicolas Posseme
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Publication number: 20160276494Abstract: A method for making a transistor in which: a) on a substrate, at least one semi-conductor structure is made, which is formed by a stack comprising alternating layer(s) based on at least one first semi-conductor material and layer(s) based on at least one second semi-conductor material different from the first semi-conductor material, b) a zone of the structure is made amorphous using implantations, the zone made amorphous comprising one or more portions of one or more layers based on the second semi-conductor material, c) the portions are removed by selectively etching a second semi-conductor material made amorphous towards the first semi-conductor material (FIG. 2L).Type: ApplicationFiled: March 15, 2016Publication date: September 22, 2016Applicant: Commissariat a l'energie atomique et aux energies alternativesInventors: Sylvain BARRAUD, Shay REBOH, Maud VINET
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Publication number: 20160268406Abstract: Single-electron transistor comprising at least: first semiconductor portions forming source and drain regions, a second semiconductor portion forming at least one quantum island, third semiconductor portions forming tunnel junctions between the second semiconductor portion and the first semiconductor portions, a gate and a gate dielectric located on at least the second semiconductor portion, in which a thickness of each of the first semiconductor portions is greater than the thickness of the second semiconductor portion, and in which a thickness of the second semiconductor portion is greater than the thickness of each of the third semiconductor portions.Type: ApplicationFiled: March 10, 2016Publication date: September 15, 2016Applicant: Commissariat a L'Energie Atomique et aux Energies AlternativesInventors: Sylvain BARRAUD, Ivan DUCHEMIN, Louis HUTIN, Yann-Michel NIQUET, Maud VINET
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Patent number: 9425255Abstract: Fabrication of a microelectronic device on a semiconductor on insulator type substrate, the device being provided with a transistor of a given type, the channel structure of which is formed from semiconducting bar(s), a dielectric area different from the insulating layer of the substrate being provided to replace the insulating layer, facing the transistor channel structure, specifically for this given type of transistor.Type: GrantFiled: December 29, 2015Date of Patent: August 23, 2016Assignees: Commissariat a l'energie atomique et aux energies alternatives, STMICROELECTRONICS (CROLLES 2) SASInventors: Sylvain Barraud, Yves Morand
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Publication number: 20160133700Abstract: Fabrication of a microelectronic device on a semiconductor on insulator type substrate, the device being provided with a transistor of a given type, the channel structure of which is formed from semiconducting bar(s), a dielectric area different from the insulating layer of the substrate being provided to replace the insulating layer, facing the transistor channel structure, specifically for this given type of transistor.Type: ApplicationFiled: December 29, 2015Publication date: May 12, 2016Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS (CROLLES 2) SASInventors: Sylvain BARRAUD, Yves MORAND
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Patent number: 9276073Abstract: Fabrication of a microelectronic device on a semiconductor on insulator type substrate, the device being provided with a transistor of a given type, the channel structure of which is formed from semiconducting bar(s), a dielectric area different from the insulating layer of the substrate being provided to replace the insulating layer, facing the transistor channel structure, specifically for this given type of transistor.Type: GrantFiled: May 1, 2014Date of Patent: March 1, 2016Assignees: Commissariat a l'énergie atomique et aux énergies alternatives, STMICROELECTRONICS (CROLLES 2) SASInventors: Sylvain Barraud, Yves Morand
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Publication number: 20150194489Abstract: A semiconductor device is provided, including two semiconductor nanowires superimposed one on top of the other or arranged next to one another, spaced one from the other and forming channel regions of the semiconductor device, a dielectric structure entirely filling a space between the nanowires and which is in contact with the nanowires, a gate dielectric and a gate covering a first of the nanowires, sidewalls of the nanowires and sidewalls of the dielectric structure when the nanowires are superimposed one on top of the other, or covering a part of the upper faces of the nanowires and a part of an upper face of the dielectric structure when the nanowires are arranged next to one another, and wherein the dielectric structure comprises a portion of dielectric material with a relative permittivity greater than or equal to 20.Type: ApplicationFiled: December 23, 2014Publication date: July 9, 2015Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALTInventors: Sylvain BARRAUD, Pierrette Rivallin, Pascal Scheiblin
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Patent number: 8969148Abstract: The present invention relates to a method for producing a microelectronic device having a channel structure formed from superimposed nanowires, in which a nanowire stack having a constant transverse section is firstly formed, followed by a sacrificial gate and insulating spacers, where source and drain areas are then formed by growth of semiconductor material on areas of the stack which are not protected by the sacrificial gate and the insulating spacers (FIG. 4D).Type: GrantFiled: April 15, 2013Date of Patent: March 3, 2015Assignee: Commissariat a l'energie atomique et aux energies alternativesInventors: Maud Vinet, Sylvain Barraud, Laurent Grenouillet
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Publication number: 20140326955Abstract: Fabrication of a microelectronic device on a semiconductor on insulator type substrate, the device being provided with a transistor of a given type, the channel structure of which is formed from semiconducting bar(s), a dielectric area different from the insulating layer of the substrate being provided to replace the insulating layer, facing the transistor channel structure, specifically for this given type of transistor.Type: ApplicationFiled: May 1, 2014Publication date: November 6, 2014Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT, STMICROELECTRONICS (CROLLES 2) SASInventors: Sylvain BARRAUD, Yves MORAND