Patents by Inventor Sylvain Clerc
Sylvain Clerc has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8837206Abstract: A memory device includes first and second inverters cross-coupled between first and second nodes. The first inverter is configured to be supplied by a first supply voltage via a first transistor and the second inverter is configured to be supplied by the first supply voltage via a second transistor. A first control circuit is configured to control a gate node of the first transistor based on the voltage at the second node and at a gate node of the second transistor. A second control circuit is configured to control the gate node of the second transistor based on the voltage at the first node and at the gate node of the first transistor.Type: GrantFiled: November 5, 2012Date of Patent: September 16, 2014Assignee: STMicroelectronics (Crolles 2)Inventors: Maximilien Glorieux, Sylvain Clerc, Gilles Gasiot, Phillippe Roche
-
Publication number: 20140176228Abstract: The invention relates to an integrated circuit comprising: a first semiconductor well (60); a plurality of standard cells (66), each standard cell comprising a first field-effect transistor in FDSOI technology comprising a first semiconductor ground plane located immediately on the first well; and a clock tree cell (30) contiguous with the standard cells, the clock tree cell comprising a second field-effect transistor in FDSOI technology, which transistor comprises a second semiconductor ground plane located immediately on the first well (60), so as to form a p-n junction with this first well. The integrated circuit comprises an electrical power supply network (51) able to apply separate electrical biases directly to the first and second ground planes.Type: ApplicationFiled: December 19, 2013Publication date: June 26, 2014Inventors: Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel, Yvain Thonnart
-
Publication number: 20140176216Abstract: The invention relates to an integrated circuit comprising: a block comprising: first (38) and second (40) oppositely doped semiconductor wells; standard cells (42, 43) placed next to one another, each standard cell (42) comprising first transistors (60, 62), and a clock tree cell (30) encircled by standard cells, the clock tree cell (30) comprising: a third semiconductor well (104) having the same doping type as the doping of the first well (38); second transistors (100, 102); a semiconductor strip (106) extending continuously around the third well (104), and having the opposite doping type to the doping of the third well, so as to electrically isolate the third well (104) from the first well (38).Type: ApplicationFiled: December 19, 2013Publication date: June 26, 2014Inventors: Yvain Thonnart, Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel
-
Patent number: 8570060Abstract: A method for protecting an electronic circuit having at least one output against external radiation includes functionally duplicating the electronic circuit and linking the outputs of the electronic circuit and the duplicated electronic circuit to homologous inputs of at least functionally equivalent combinatorial or sequential elements. The homologous outputs of all the combinatorial or sequential elements are linked together. The electronic circuit can be duplicated multiple times.Type: GrantFiled: May 19, 2011Date of Patent: October 29, 2013Assignee: STMicroelectronics SAInventors: Sylvain Clerc, Fabian Firmin, Philippe Roche
-
Patent number: 8565030Abstract: A read boost circuit arranged to boost the voltage difference between a pair of complementary bit lines of a memory device during a read operation, the read boost circuit including: a first transistor adapted to be controlled by the voltage level on a first bit line of the pair of bit lines to couple a second bit line of the pair of bit lines to a first supply voltage; and a second transistor connected directly to ground and adapted to be controlled by the voltage level on the second bit line to couple the first bit line to ground.Type: GrantFiled: September 22, 2011Date of Patent: October 22, 2013Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS, Centre National de la Recherche ScientifiqueInventors: Fady Abouzeid, Sylvain Clerc, Philippe Roche
-
Patent number: 8497701Abstract: The present invention relates to an integrated electronic circuit including elements enabling to implement a logic function and means for attenuating the sensitivity of said elements to external disturbances, said attenuation means being disconnectable during phases of intentional modification of the state of said elements.Type: GrantFiled: November 18, 2011Date of Patent: July 30, 2013Assignee: STMicroelectronics (Crolles 2) SASInventors: Sylvain Clerc, Gilles Gasiot, Maximilien Glorieux
-
Publication number: 20130051131Abstract: A device and a method for controlling an SRAM-type device, including: a bistable circuit and two switching circuits respectively connecting two access terminals of the bistable circuit to two complementary bit lines in a first direction, each switching circuit including a first switch and a second switch in series between one of the bit lines and one of the access terminals, the control terminal of the second switch being connected to a word control line in the first direction; and a third switch between the midpoint of the series connection and a terminal of application of a reference potential, a control terminal of the third switch being connected to the other one of the access terminals.Type: ApplicationFiled: February 14, 2011Publication date: February 28, 2013Applicants: ST Microelectronics (Crolles 2) SAS, ST Microelectronics S.A.Inventors: Fady Abouzeid, Sylvain Clerc
-
Publication number: 20130009665Abstract: The present invention relates to an integrated electronic circuit including elements enabling to implement a logic function and means for attenuating the sensitivity of said elements to external disturbances, said attenuation means being disconnectable during phases of intentional modification of the state of said elements.Type: ApplicationFiled: November 18, 2011Publication date: January 10, 2013Applicant: STMicroelectronics SAS (Crolles)Inventors: Sylvain Clerc, Gilles Gasiot, Maximillen Glorieux
-
Patent number: 8339172Abstract: A flip-flop may include a first master stage for latching data, a second slave stage for latching data, and an input multiplexer circuit receiving, as input, data to be latched in the flip-flop. The multiplexer may have single clock phase. The first master stage may be clocked based upon a clock phase, whereas the second stage may be clocked based upon another clock phase.Type: GrantFiled: October 7, 2010Date of Patent: December 25, 2012Assignee: STMicroelectronics SAInventors: Fabian Firmin, Sylvain Clerc, Jean-Pierre Schoellkopf, Fady Abouzeid
-
Publication number: 20120081978Abstract: A read boost circuit arranged to boost the voltage difference between a pair of complementary bit lines of a memory device during a read operation, the read boost circuit including: a first transistor adapted to be controlled by the voltage level on a first bit line of the pair of bit lines to couple a second bit line of the pair of bit lines to a first supply voltage; and a second transistor connected directly to ground and adapted to be controlled by the voltage level on the second bit line to couple the first bit line to ground.Type: ApplicationFiled: September 22, 2011Publication date: April 5, 2012Applicants: STMicroelectronics S.A., Centre National de la Recherche Scientifique, STMicroelectronics Crolles 2 SASInventors: Fady Abouzeid, Sylvain Clerc, Philippe Roche
-
Publication number: 20120042292Abstract: A method of synthesis of at least one logic device coupled between first and second supply voltages and having a plurality of inputs and an output, the logic device including a plurality of transistors having a standard gate length, the method including: identifying, in the at least one logic device, one or more transistors connected between the first or second supply voltage and the output node; and increasing the gate length of each of the identified one or more transistors.Type: ApplicationFiled: August 10, 2010Publication date: February 16, 2012Applicants: STMicroelectronics S.A., Centre National de la Recherche Scientifique, STMicroelectronics (Crolles 2) SASInventors: Fady Abouzeid, Sylvain Clerc, Fabian Firmin
-
Publication number: 20110291696Abstract: A method for protecting an electronic circuit having at least one output against external radiation includes functionally duplicating the electronic circuit and linking the outputs of the electronic circuit and the duplicated electronic circuit to homologous inputs of at least functionally equivalent combinatorial or sequential elements. The homologous outputs of all the combinatorial or sequential elements are linked together. The electronic circuit can be duplicated multiple times.Type: ApplicationFiled: May 19, 2011Publication date: December 1, 2011Applicant: STMicroelectronics SAInventors: Sylvain Clerc, Fabian Firmin, Philippe Roche
-
Publication number: 20110084748Abstract: A flip-flop may include a first master stage for latching data, a second slave stage for latching data, and an input multiplexer circuit receiving, as input, data to be latched in the flip-flop. The multiplexer may have single clock phase. The first master stage may be clocked based upon a clock phase, whereas the second stage may be clocked based upon another clock phase.Type: ApplicationFiled: October 7, 2010Publication date: April 14, 2011Applicant: STMicroelectronics SAInventors: Fabian Firmin, Sylvain Clerc, Jean-Pierre Schoellkopf, Fady Abouzeid
-
Patent number: 7876141Abstract: A generator of synchronization pulses intended for at least two registers, including a first input intended to receive a clock signal and at least one output intended to deliver the pulses on the clock input of said registers, and at least one second input intended to receive a signal for forcing the output, independently from the clock signal, to make said registers transparent.Type: GrantFiled: October 14, 2008Date of Patent: January 25, 2011Assignees: STMicroelectronics Inc., STMicroelectronics S.A.Inventors: Benoît Lasbouygues, Sylvain Clerc, Alain Artieri, Thomas Zounes, Françoise Jacquet
-
Patent number: 7564282Abstract: A bistable flip-flop device is provided that is triggered on the edges of a clock signal. The device has an active mode in which it is electrically powered and an inactive mode. The device includes a chain of inverters controlled by a clock signal, storage means for storing the state of the device in the active mode, and retention means for storing the state of the device in the inactive mode. The device includes a continuously-powered bistable structure that integrates the retention means and part of the storage means. The bistable structure includes a single isolation switch connected to the inverter chain and controlled by a standby logic signal that is representative of the active or inactive mode.Type: GrantFiled: October 26, 2005Date of Patent: July 21, 2009Assignee: STMicroelectronics SAInventor: Sylvain Clerc
-
Publication number: 20090146720Abstract: A generator of synchronization pulses intended for at least two registers, including a first input intended to receive a clock signal and at least one output intended to deliver the pulses on the clock input of said registers, and at least one second input intended to receive a signal for forcing the output, independently from the clock signal, to make said registers transparent.Type: ApplicationFiled: October 14, 2008Publication date: June 11, 2009Applicants: STMicroelectronics Inc., STMicroelectronics S.A.Inventors: Benoit Lasbouygues, Sylvain Clerc, Alain Artieri, Thomas Zounes, Francoise Jacquet
-
Patent number: 7321506Abstract: The multivibrator is protected against current or voltage spikes and includes a first data transfer port that receives, as input, multivibrator input data, and a first/master latch cell connected on the output side of the first transfer port. A second/slave latch cell is included, and a second data transfer port is placed between the first and second latch cells. Each latch cell includes a set of redundant data storage nodes. The transfer ports each circuits/devices for writing data separately into each storage node.Type: GrantFiled: April 21, 2006Date of Patent: January 22, 2008Assignee: STMicroelectronics SAInventors: Philippe Roche, Francois Jacquet, Sylvain Clerc
-
Patent number: 7236031Abstract: A bistable circuit includes a first inverter and a capacitive inversion circuit having one input coupled to an output of the first inverter. The capacitive inversion circuit includes a second inverter and a capacitive circuit parallel-coupled to the input and an output of the capacitive inversion circuit. The bistable circuit also includes a switch to isolate the output of the capacitive inversion circuit from an input of the first inverter when the switch receives an active validation signal or, if not, to couple the output of the capacitive inversion circuit to the input of the first inverter.Type: GrantFiled: June 23, 2005Date of Patent: June 26, 2007Assignee: STMicroelectronics SAInventors: Sylvain Clerc, Philippe Roche, Francois Jacquet
-
Publication number: 20060255870Abstract: The multivibrator is protected against current or voltage spikes and includes a first data transfer port that receives, as input, multivibrator input data, and a first/master latch cell connected on the output side of the first transfer port. A second/slave latch cell is included, and a second data transfer port is placed between the first and second latch cells. Each latch cell includes a set of redundant data storage nodes. The transfer ports each circuits/devices for writing data separately into each storage node.Type: ApplicationFiled: April 21, 2006Publication date: November 16, 2006Applicant: STMicroelectronics SAInventors: Philippe Roche, Francois Jacquet, Sylvain Clerc
-
Publication number: 20060109040Abstract: A bistable flip-flop device is provided that is triggered on the edges of a clock signal. The device has an active mode in which it is electrically powered and an inactive mode. The device includes a chain of inverters controlled by a clock signal, storage means for storing the state of the device in the active mode, and retention means for storing the state of the device in the inactive mode. The device includes a continuously-powered bistable structure that integrates the retention means and part of the storage means. The bistable structure includes a single isolation switch connected to the inverter chain and controlled by a standby logic signal that is representative of the active or inactive mode.Type: ApplicationFiled: October 26, 2005Publication date: May 25, 2006Applicant: STMICROELECTRONICS SAInventor: Sylvain Clerc