Patents by Inventor Sylvain Leomant

Sylvain Leomant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10868172
    Abstract: A semiconductor device includes: a gate trench extending into a Si substrate; a body region in the Si substrate, the body region including a vertical channel region adjacent a sidewall of the gate trench; a source region in the Si substrate above the body region; a contact trench extending into the Si substrate and separated from the gate trench by a portion of the source region and by a portion of the body region; an electrically conductive material in the contact trench; and a diffusion barrier structure interposed between a sidewall of the contact trench and the vertical channel region, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si and configured to increase carrier mobility within the vertical channel region. Corresponding methods of manufacture are also described.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: December 15, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Blank, Thomas Feil, Maximilian Roesch, Martin Poelzl, Robert Haase, Sylvain Leomant, Bernhard Goller, Andreas Meiser
  • Patent number: 10861966
    Abstract: A semiconductor device includes: a gate trench extending into a Si substrate; a body region in the Si substrate adjacent the gate trench; a source region in the Si substrate above the body region; a diffusion barrier structure adjacent a sidewall of the gate trench, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si; and a channel region formed in the Si capping layer and which vertically extends along the sidewall of the gate trench. Corresponding methods of manufacture are also described.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: December 8, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Feil, Robert Haase, Martin Poelzl, Maximilian Roesch, Sylvain Leomant, Bernhard Goller, Ravi Keshav Joshi
  • Publication number: 20200350401
    Abstract: A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si.
    Type: Application
    Filed: July 16, 2020
    Publication date: November 5, 2020
    Inventors: Martin Poelzl, Robert Haase, Sylvain Leomant, Maximilian Roesch, Ravi Keshav Joshi, Andreas Meiser, Xiaoqiu Huang, Ling Ma
  • Patent number: 10790353
    Abstract: A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: September 29, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Poelzl, Robert Haase, Sylvain Leomant, Maximilian Roesch, Ravi Keshav Joshi, Andreas Meiser, Xiaoqiu Huang, Ling Ma
  • Publication number: 20200303498
    Abstract: A method of manufacturing a semiconductor device includes: forming one or more device epitaxial layers over a main surface of a doped Si base substrate; forming a diffusion barrier structure including alternating layers of Si and oxygen-doped Si in an upper part of the doped Si base substrate adjacent the main surface of the doped Si base substrate, in a lower part of the one or more device epitaxial layers adjacent the main surface of the doped Si base substrate, or in one or more additional epitaxial layers disposed between the main surface of the doped Si base substrate and the one or more device epitaxial layers; and forming a gate above the diffusion barrier structure.
    Type: Application
    Filed: June 9, 2020
    Publication date: September 24, 2020
    Inventors: Martin Poelzl, Robert Haase, Maximilian Roesch, Sylvain Leomant, Andreas Meiser, Bernhard Goller, Ravi Keshav Joshi
  • Patent number: 10741638
    Abstract: A semiconductor device includes a doped Si base substrate, one or more device epitaxial layers formed over a main surface of the doped Si base substrate, a diffusion barrier structure, and a gate formed above the diffusion barrier structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si formed in an upper part of the doped Si base substrate adjacent the main surface of the doped Si base substrate, in a lower part of the one or more device epitaxial layers adjacent the main surface of the doped Si base substrate, or in one or more additional epitaxial layers disposed between the main surface of the doped Si base substrate and the one or more device epitaxial layers.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: August 11, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Poelzl, Robert Haase, Maximilian Roesch, Sylvain Leomant, Andreas Meiser, Bernhard Goller, Ravi Keshav Joshi
  • Publication number: 20200152733
    Abstract: A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si.
    Type: Application
    Filed: November 9, 2018
    Publication date: May 14, 2020
    Inventors: Martin Poelzl, Robert Haase, Sylvain Leomant, Maximilian Roesch, Ravi Keshav Joshi, Andreas Meiser, Xiaoqiu Huang, Ling Ma
  • Publication number: 20200127135
    Abstract: A semiconductor device includes: a gate trench extending into a Si substrate; a body region in the Si substrate adjacent the gate trench; a source region in the Si substrate above the body region; a diffusion barrier structure adjacent a sidewall of the gate trench, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si; and a channel region formed in the Si capping layer and which vertically extends along the sidewall of the gate trench. Corresponding methods of manufacture are also described.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Inventors: Thomas Feil, Robert Haase, Martin Poelzl, Maximilian Roesch, Sylvain Leomant, Bernhard Goller, Ravi Keshav Joshi
  • Publication number: 20200127134
    Abstract: A semiconductor device includes: a gate trench extending into a Si substrate; a body region in the Si substrate, the body region including a vertical channel region adjacent a sidewall of the gate trench; a source region in the Si substrate above the body region; a contact trench extending into the Si substrate and separated from the gate trench by a portion of the source region and by a portion of the body region; an electrically conductive material in the contact trench; and a diffusion barrier structure interposed between a sidewall of the contact trench and the vertical channel region, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si and configured to increase carrier mobility within the vertical channel region. Corresponding methods of manufacture are also described.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Inventors: Oliver Blank, Thomas Feil, Maximilian Roesch, Martin Poelzl, Robert Haase, Sylvain Leomant, Bernhard Goller, Andreas Meiser
  • Publication number: 20200083335
    Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a first major surface, a trench extending from the first major surface into the semiconductor substrate and having a base and a side wall extending form the base to the first major surface, and a field plate arranged in the trench and an enclosed cavity in the trench. The enclosed cavity is defined by insulating material and is laterally positioned between a side wall of the field plate and the side wall of the trench.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 12, 2020
    Inventors: Sylvain Leomant, Georg Ehrentraut, Maximilian Roesch
  • Patent number: 10580888
    Abstract: A semiconductor device includes a gate trench extending into a Si substrate, a body region in the Si substrate, the body region including a channel region which extends along a sidewall of the gate trench, a source region in the Si substrate above the body region, a contact trench extending into the Si substrate and separated from the gate trench by a portion of the source region and a portion of the body region, the contact trench being filled with an electrically conductive material which contacts the source region at a sidewall of the contact trench and a highly doped body contact region at a bottom of the contact trench, and a diffusion barrier structure formed along the sidewall of the contact trench and disposed between the highly doped body contact region and the channel region, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: March 3, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Blank, Thomas Feil, Maximilian Roesch, Martin Poelzl, Robert Haase, Sylvain Leomant, Bernhard Goller, Andreas Meiser
  • Patent number: 10573742
    Abstract: A semiconductor device includes a gate trench extending into a Si substrate, a body region in the Si substrate adjacent the gate trench, a source region in the Si substrate above the body region, a contact trench extending into the Si substrate and filled with an electrically conductive material which contacts the source region at a sidewall of the contact trench and a highly doped body contact region at a bottom of the contact trench, a diffusion barrier structure formed along the sidewall of the gate trench, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si, and a channel region formed in the Si capping layer and which vertically extends along the sidewall of the gate trench. Corresponding methods of manufacture are also described.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: February 25, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Feil, Robert Haase, Martin Poelzl, Maximilian Roesch, Sylvain Leomant, Bernhard Goller, Ravi Keshav Joshi
  • Publication number: 20200052066
    Abstract: A semiconductor device includes a doped Si base substrate, one or more device epitaxial layers formed over a main surface of the doped Si base substrate, a diffusion barrier structure, and a gate formed above the diffusion barrier structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si formed in an upper part of the doped Si base substrate adjacent the main surface of the doped Si base substrate, in a lower part of the one or more device epitaxial layers adjacent the main surface of the doped Si base substrate, or in one or more additional epitaxial layers disposed between the main surface of the doped Si base substrate and the one or more device epitaxial layers.
    Type: Application
    Filed: August 8, 2018
    Publication date: February 13, 2020
    Inventors: Martin Poelzl, Robert Haase, Maximilian Roesch, Sylvain Leomant, Andreas Meiser, Bernhard Goller, Ravi Keshav Joshi
  • Publication number: 20200052109
    Abstract: A semiconductor device includes a gate trench extending into a Si substrate, a body region in the Si substrate, the body region including a channel region which extends along a sidewall of the gate trench, a source region in the Si substrate above the body region, a contact trench extending into the Si substrate and separated from the gate trench by a portion of the source region and a portion of the body region, the contact trench being filled with an electrically conductive material which contacts the source region at a sidewall of the contact trench and a highly doped body contact region at a bottom of the contact trench, and a diffusion barrier structure formed along the sidewall of the contact trench and disposed between the highly doped body contact region and the channel region, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si.
    Type: Application
    Filed: August 8, 2018
    Publication date: February 13, 2020
    Inventors: Oliver Blank, Thomas Feil, Maximilian Roesch, Martin Poelzl, Robert Haase, Sylvain Leomant, Bernhard Goller, Andreas Meiser
  • Publication number: 20200052110
    Abstract: A semiconductor device includes a gate trench extending into a Si substrate, a body region in the Si substrate adjacent the gate trench, a source region in the Si substrate above the body region, a contact trench extending into the Si substrate and filled with an electrically conductive material which contacts the source region at a sidewall of the contact trench and a highly doped body contact region at a bottom of the contact trench, a diffusion barrier structure formed along the sidewall of the gate trench, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si, and a channel region formed in the Si capping layer and which vertically extends along the sidewall of the gate trench. Corresponding methods of manufacture are also described.
    Type: Application
    Filed: August 8, 2018
    Publication date: February 13, 2020
    Inventors: Thomas Feil, Robert Haase, Martin Poelzl, Maximilian Roesch, Sylvain Leomant, Bernhard Goller, Ravi Keshav Joshi
  • Patent number: 10510836
    Abstract: A semiconductor device includes a gate trench extending into a Si substrate, the gate trench including a gate electrode and a gate dielectric separating the gate electrode from the Si substrate. The semiconductor device further includes a body region in the Si substrate adjacent the gate trench, the body region including a channel region which extends along a sidewall of the gate trench, a source region in the Si substrate above the body region, a contact trench extending into the Si substrate and filled with an electrically conductive material which contacts the source region and a highly doped body contact region at a bottom of the contact trench, and a diffusion barrier structure extending along at least part of the channel region and disposed between the channel region and the highly doped body contact region. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: December 17, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Robert Haase, Martin Poelzl, Maximilian Roesch, Sylvain Leomant, Andreas Meiser
  • Publication number: 20190371899
    Abstract: A transistor device includes a first trench and a second trench arranged in a comb-like structure, first sections of the first and second trenches corresponding to teeth of the comb-like structure and second sections of the first and second trenches corresponding to opposing shafts of the comb-like structure. The arrangement of the first trench and the second trench forms a pattern of interdigitated fingers. Transistor cells of the transistor device are disposed between single fingers of the first and second trenches. A semiconductor mesa separates the first trench and the second trench from each other. A gate electrode in the first trench or a gate electrode in the second trench is electrically connected to a source potential instead of a gate potential to decrease a gate charge of the transistor device.
    Type: Application
    Filed: August 8, 2019
    Publication date: December 5, 2019
    Inventors: Britta Wutte, Sylvain Leomant
  • Patent number: 10418452
    Abstract: A semiconductor device includes a first trench and a second trench in a first main surface of a semiconductor substrate. Each of the first and second trenches includes first sections extending lengthwise in a first direction and a second section extending lengthwise in a second direction transvers to the first direction, the second section of the first trench being disposed opposite to the second section of the second trench. The semiconductor device further includes a semiconductor mesa separating the first and second trenches, and a source metal layer above the first main surface of the semiconductor substrate and electrically connected to source regions in the semiconductor mesa. Corresponding methods of manufacture are also described.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: September 17, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Britta Wutte, Sylvain Leomant
  • Publication number: 20180226481
    Abstract: A semiconductor device includes a first trench and a second trench in a first main surface of a semiconductor substrate. Each of the first and second trenches includes first sections extending lengthwise in a first direction and a second section extending lengthwise in a second direction transvers to the first direction, the second section of the first trench being disposed opposite to the second section of the second trench. The semiconductor device further includes a semiconductor mesa separating the first and second trenches, and a source metal layer above the first main surface of the semiconductor substrate and electrically connected to source regions in the semiconductor mesa. Corresponding methods of manufacture are also described.
    Type: Application
    Filed: April 9, 2018
    Publication date: August 9, 2018
    Inventors: Britta Wutte, Sylvain Leomant
  • Patent number: 9941354
    Abstract: A semiconductor device includes a first gate trench and a second gate trench in a first main surface of a semiconductor substrate. A mesa is arranged between the first gate trench and the second gate trench. The mesa separates the first gate trench from the second gate trench. Each of the first and second gate trenches includes first sections extending in a first direction and second sections connecting adjacent ones of the first sections. The second sections of the first gate trench are disposed opposite to the second sections of the second gate trench with respect to a plane perpendicular to the first direction.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: April 10, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Britta Wutte, Sylvain Leomant