Patents by Inventor Syrus Ziai

Syrus Ziai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105762
    Abstract: A semiconductor device has a package substrate, a system-on-chip (SoC) die, and a power management integrated circuit (PMIC) die, arranged in a vertical stack. The SoC die is disposed on a first surface of the package substrate, and the PMIC die is mechanically coupled to a second surface of the package substrate. The PMIC die is electrically coupled to the SOC die via first via connectors of the package substrate and configured to provide DC power to the SOC die via DC connectors electrically coupled to the via connectors of the package substrate. The PMIC die includes thin film inductors, corresponding to the DC connectors, on a surface of the PMIC die and located adjacent to the second surface of the package substrate.
    Type: Application
    Filed: December 6, 2023
    Publication date: March 28, 2024
    Inventors: Peng Zou, Syrus Ziai
  • Patent number: 11893242
    Abstract: Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a common substrate and a first integrated circuit (IC) chip disposed on the common substrate. The first IC chip includes a first memory interface. A second IC chip is disposed on the common substrate and includes a second memory interface. A first memory device is disposed on the common substrate and includes memory and a first port coupled to the memory. The first port is configured for communicating with the first memory interface of the first IC chip. A second port is coupled to the memory and communicates with the second memory interface of the second IC chip. In-memory processing circuitry is coupled to the memory and controls transactions between the first memory device and the first and second IC chips.
    Type: Grant
    Filed: November 25, 2022
    Date of Patent: February 6, 2024
    Assignee: Eliyan Corporation
    Inventors: Ramin Farjadrad, Syrus Ziai
  • Patent number: 11881783
    Abstract: An electronic device has a power rail that is driven by voltage regulators and provides a rail voltage. Each voltage regulator has an output interface electrically coupled to the power rail to deliver up to a predefined regulator current to the power rail. In each voltage regulator, a voltage regulator controller has an input coupled to the output interface by a feedback path and controls a drive path coupled to the output interface. A bypass unit is coupled to the drive path and voltage regulator controller and operates in a standby mode or an operational mode. In the standby mode, the bypass unit bypasses the feedback path and the respective voltage regulator does not deliver current to the power rail, while in the operational mode, the bypass unit does not bypass the feedback path and the respective voltage regulator delivers up to the predefined regulator current to the power rail.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: January 23, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Peng Zou, Xijian Lin, Gang Ren, Joseph Dibene, Syrus Ziai
  • Patent number: 11855043
    Abstract: A multi-chip module (MCM) includes a common substrate and first and second integrated circuit (IC) chips disposed on the common substrate. The first integrated circuit (IC) chip includes a first interface circuit disposed proximate a first edge of the first IC chip and a second interface circuit disposed proximate the first edge of the first IC chip. A first chiplet couples to the first interface circuit via a first link. A second chiplet couples to the second interface circuit via a second link. A first position of the first chiplet with respect to the first IC chip is staggered in a longitudinal dimension relative to a second position of the second chiplet with respect to the first IC chip.
    Type: Grant
    Filed: November 25, 2022
    Date of Patent: December 26, 2023
    Assignee: Eliyan Corporation
    Inventors: Ramin Farjadrad, Syrus Ziai
  • Patent number: 11855124
    Abstract: A semiconductor device has a package substrate, a system-on-chip (SoC) die, and a power management integrated circuit (PMIC) die, arranged in a vertical stack. The SoC die is disposed on a first surface of the package substrate, and the PMIC die is mechanically coupled to a second surface of the package substrate. The PMIC die is electrically coupled to the SOC die via first via connectors of the package substrate and configured to provide DC power to the SOC die via DC connectors electrically coupled to the via connectors of the package substrate. The PMIC die includes thin film inductors, corresponding to the DC connectors, on a surface of the PMIC die and located adjacent to the second surface of the package substrate.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: December 26, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Peng Zou, Syrus Ziai
  • Publication number: 20230387181
    Abstract: A semiconductor device has a package substrate, a system-on-chip (SoC) die, and a power management integrated circuit (PMIC) die, arranged in a vertical stack. The SoC die is disposed on a first surface of the package substrate, and the PMIC die is mechanically coupled to a second surface of the package substrate. The PMIC die is electrically coupled to the SOC die via first via connectors of the package substrate and configured to provide DC power to the SOC die via DC connectors electrically coupled to the via connectors of the package substrate. The PMIC die includes thin film inductors, corresponding to the DC connectors, on a surface of the PMIC die and located adjacent to the second surface of the package substrate.
    Type: Application
    Filed: April 13, 2023
    Publication date: November 30, 2023
    Inventors: Peng ZOU, Syrus ZIAI
  • Publication number: 20230266449
    Abstract: A method transmits a predetermined signal through a first channel that includes a first digital circuit to produce a first result. The first channel is a functional channel in the FMCW LIDAR system. The method retrieves a second result that is based on the predetermined signal, and determines whether the first result and the second result are nonequivalent. The method then invokes a fault signal in response to determining that the first result and the second result are nonequivalent.
    Type: Application
    Filed: January 31, 2023
    Publication date: August 24, 2023
    Inventors: Syrus Ziai, Kumar Bhargav Viswanatha, Amol V. Gole, Murat Ozbas, Mark Pude, Esha John
  • Publication number: 20230217841
    Abstract: An electronic device (e.g., a diode) is provided that includes a substrate and a patterned layer of superconducting material disposed over the substrate. The patterned layer forms a first electrode, a second electrode, and a loop coupling the first electrode with the second electrode by a first channel and a second channel. The first channel and the second channel have different minimum widths. For a range of current magnitudes, when a magnetic field is applied to the patterned layer of superconducting material, the conductance from the first electrode to the second electrode is greater than the conductance from the second electrode to the first electrode.
    Type: Application
    Filed: November 14, 2022
    Publication date: July 6, 2023
    Inventors: Faraz Najafi, Syrus Ziai
  • Patent number: 11671017
    Abstract: A semiconductor device has a power rail that provides a rail voltage. The power rail is electrically coupled to a plurality of voltage regulators, and each voltage regulator includes an output interface electrically coupled to the power rail, and a first drive path and a second drive path both coupled to the output interface, and an intra-regulator balancing circuit. The first and second drive paths are coupled in parallel with each other, and operate during a first phase and a second phase, at an operating frequency, to provide a first path current and a second path current to the power rail, respectively. The intra-regulator balancing circuit senses the first and second path currents and controls a first duty cycle of the first phase and/or a second duty cycle of the second phase based on a difference of the first and second path currents.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: June 6, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Gang Ren, Peng Zou, Syrus Ziai, Curtis Roger McAllister
  • Patent number: 11658577
    Abstract: A semiconductor device includes a plurality of voltage regulators arranged in a field programmable array and a power array controller coupled to the plurality of voltage regulators. The power array controller is configured to control the plurality of voltage regulators to output power to a plurality of power rails. Each power rail provides a respective rail current at a respective rail voltage. The power array controller is configured to for each of the plurality of power rails, determine the respective rail current associated with the respective power rail, select a subset of voltage regulators according to at least the respective rail current, and enable the subset of voltage regulators to generate the respective rail voltage and provide the respective rail current collectively.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: May 23, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Peng Zou, Gang Ren, Syrus Ziai, Curtis Roger McAllister
  • Publication number: 20230065469
    Abstract: An electronic device has a power rail that is driven by voltage regulators and provides a rail voltage. Each voltage regulator has an output interface electrically coupled to the power rail to deliver up to a predefined regulator current to the power rail. In each voltage regulator, a voltage regulator controller has an input coupled to the output interface by a feedback path and controls a drive path coupled to the output interface. A bypass unit is coupled to the drive path and voltage regulator controller and operates in a standby mode or an operational mode. In the standby mode, the bypass unit bypasses the feedback path and the respective voltage regulator does not deliver current to the power rail, while in the operational mode, the bypass unit does not bypass the feedback path and the respective voltage regulator delivers up to the predefined regulator current to the power rail.
    Type: Application
    Filed: March 1, 2022
    Publication date: March 2, 2023
    Inventors: Peng Zou, Xijian Lin, Gang Ren, Joseph Dibene, Syrus Ziai
  • Patent number: 11502237
    Abstract: An electronic device (e.g., a diode) is provided that includes a substrate and a patterned layer of superconducting material disposed over the substrate. The patterned layer forms a first electrode, a second electrode, and a loop coupling the first electrode with the second electrode by a first channel and a second channel. The first channel and the second channel have different minimum widths. For a range of current magnitudes, when a magnetic field is applied to the patterned layer of superconducting material, the conductance from the first electrode to the second electrode is greater than the conductance from the second electrode to the first electrode.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: November 15, 2022
    Assignee: PSIQUANTUM CORP.
    Inventors: Faraz Najafi, Syrus Ziai
  • Patent number: 11441941
    Abstract: A superconductor device is manufactured by depositing a barrier layer over a substrate including silicon, the barrier layer including silicon and nitrogen; depositing a seed layer for a superconductor layer over the barrier layer, the seed layer including aluminum and nitrogen; depositing the superconductor layer over the seed layer, the superconductor layer including a layer of a superconductor material, the barrier layer serving as an oxidation barrier between the layer superconductor material and the substrate; and depositing a silicon cap layer over the superconductor layer. In some embodiments, the superconductor device includes a waveguide and a metal contact at a sufficient distance from the waveguide to prevent optical coupling between the metal contact and the waveguide.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: September 13, 2022
    Assignee: PSIQUANTUM CORP.
    Inventors: Chia-Jung Chung, Faraz Najafi, George Kovall, Vitor R. Manfrinato, Vimal Kamineni, Mark Thompson, Syrus Ziai
  • Publication number: 20220260861
    Abstract: A method includes receiving input light having an input wavelength in a first optical resonator for causing resonance of the input light in the first optical resonator. The first optical resonator includes a non-linear optical medium. The method also includes converting at least a portion of the input light to a combination of first output light having a first output wavelength that is different from the input wavelength and second output light having a second output wavelength that is different from the input wavelength and the first output wavelength by passing the input light through the non-linear optical medium. The method further includes causing resonance of the first output light and the second output light in a second optical resonator. A portion of the first optical resonator is coupled to a portion of the second optical resonator.
    Type: Application
    Filed: September 28, 2021
    Publication date: August 18, 2022
    Inventors: Damien BONNEAU, Mark THOMPSON, Syrus ZIAI
  • Publication number: 20220247315
    Abstract: A semiconductor device has a power rail that provides a rail voltage. The power rail is electrically coupled to a plurality of voltage regulators, and each voltage regulator includes an output interface electrically coupled to the power rail, and a first drive path and a second drive path both coupled to the output interface, and an intra-regulator balancing circuit. The first and second drive paths are coupled in parallel with each other, and operate during a first phase and a second phase, at an operating frequency, to provide a first path current and a second path current to the power rail, respectively. The intra-regulator balancing circuit senses the first and second path currents and controls a first duty cycle of the first phase and/or a second duty cycle of the second phase based on a difference of the first and second path currents.
    Type: Application
    Filed: November 23, 2021
    Publication date: August 4, 2022
    Inventors: Gang Ren, Peng Zou, Syrus Ziai, Curtis Roger McAllister
  • Publication number: 20220247314
    Abstract: A semiconductor device includes a plurality of voltage regulators arranged in a field programmable array and a power array controller coupled to the plurality of voltage regulators. The power array controller is configured to control the plurality of voltage regulators to output power to a plurality of power rails. Each power rail provides a respective rail current at a respective rail voltage. The power array controller is configured to for each of the plurality of power rails, determine the respective rail current associated with the respective power rail, select a subset of voltage regulators according to at least the respective rail current, and enable the subset of voltage regulators to generate the respective rail voltage and provide the respective rail current collectively.
    Type: Application
    Filed: November 23, 2021
    Publication date: August 4, 2022
    Inventors: Peng Zou, Gang Ren, Syrus Ziai, Curtis Roger McAllister
  • Publication number: 20210408356
    Abstract: An electronic device (e.g., a diode) is provided that includes a substrate and a patterned layer of superconducting material disposed over the substrate. The patterned layer forms a first electrode, a second electrode, and a loop coupling the first electrode with the second electrode by a first channel and a second channel. The first channel and the second channel have different minimum widths. For a range of current magnitudes, when a magnetic field is applied to the patterned layer of superconducting material, the conductance from the first electrode to the second electrode is greater than the conductance from the second electrode to the first electrode.
    Type: Application
    Filed: December 7, 2020
    Publication date: December 30, 2021
    Inventors: Faraz Najafi, Syrus Ziai
  • Publication number: 20210384878
    Abstract: A system includes a plurality of superconducting wires connected in parallel with one another. The plurality of superconducting wires includes a first superconducting wire and a second superconducting wire. The plurality of superconducting wires are configured to, while receiving a bias current provided to the parallel combination of the plurality of superconducting wires, operate in a superconducting state in the absence of a trigger current. The first superconducting wire is configured to, while receiving the bias current, transition to a non-superconducting state in response to receiving the trigger current. The second superconducting wire is configured to, while receiving the bias current, transition to a non-superconducting state in response to the first superconducting wire transitioning to the non-superconducting state.
    Type: Application
    Filed: January 15, 2021
    Publication date: December 9, 2021
    Inventors: Faraz Najafi, Syrus Ziai, Qiaodan Jin Stone
  • Patent number: 11163180
    Abstract: A method includes receiving input light having an input wavelength in a first optical resonator for causing resonance of the input light in the first optical resonator. The first optical resonator includes a non-linear optical medium. The method also includes converting at least a portion of the input light to a combination of first output light having a first output wavelength that is different from the input wavelength and second output light having a second output wavelength that is different from the input wavelength and the first output wavelength by passing the input light through the non-linear optical medium. The method further includes causing resonance of the first output light and the second output light in a second optical resonator. A portion of the first optical resonator is coupled to a portion of the second optical resonator.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: November 2, 2021
    Assignee: PsiQuantum Corp.
    Inventors: Damien Bonneau, Mark Thompson, Syrus Ziai
  • Publication number: 20210239518
    Abstract: A superconductor device is manufactured by depositing a barrier layer over a substrate including silicon, the barrier layer including silicon and nitrogen; depositing a seed layer for a superconductor layer over the barrier layer, the seed layer including aluminum and nitrogen; depositing the superconductor layer over the seed layer, the superconductor layer including a layer of a superconductor material, the barrier layer serving as an oxidation barrier between the layer superconductor material and the substrate; and depositing a silicon cap layer over the superconductor layer. In some embodiments, the superconductor device includes a waveguide and a metal contact at a sufficient distance from the waveguide to prevent optical coupling between the metal contact and the waveguide.
    Type: Application
    Filed: April 15, 2021
    Publication date: August 5, 2021
    Inventors: Chia-Jung Chung, Faraz Najafi, George Kovall, Vitor R. Manfrinato, Vimal Kamineni, Mark Thompson, Syrus Ziai