Patents by Inventor Syun-Ming Jang

Syun-Ming Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10854729
    Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.
    Type: Grant
    Filed: September 22, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsan-Chun Wang, Ziwei Fang, Chii-Horng Li, Tze-Liang Lee, Chao-Cheng Chen, Syun-Ming Jang
  • Publication number: 20200335404
    Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 22, 2020
    Inventors: Da-Yuan LEE, Hung-Chin CHUNG, Hsien-Ming LEE, Kuan-Ting LIU, Syun-Ming JANG, Weng CHANG, Wei-Jen LO
  • Patent number: 10756199
    Abstract: An embodiment fin field-effect-transistor (finFET) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of the channel region. The gate oxide includes a thinnest portion having a first thickness and a thickest portion having a second thickness different than the first thickness. A difference between the first thickness and the second thickness is less than a maximum thickness variation, and the maximum thickness variation is in accordance with an operating voltage of the finFET.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chen, Meng-Shu Lin, Liang-Yin Chen, Xiong-Fei Yu, Syun-Ming Jang, Hui-Cheng Chang
  • Patent number: 10699966
    Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Da-Yuan Lee, Hung-Chin Chung, Hsien-Ming Lee, Kuan-Ting Liu, Syun-Ming Jang, Weng Chang, Wei-Jen Lo
  • Publication number: 20200098588
    Abstract: An ashing process and device forms radicals of an ashing gas through a secondary reaction. A plasma is generated from a first gas, which is diffused through a first gas distribution plate (GDP). The plasma is diffused through a second GDP and a second gas is supplied below the second GDP. The first gas reacts with the second gas to energize the second gas. The energized second gas is used in ashing a resist layer from a substrate.
    Type: Application
    Filed: November 27, 2019
    Publication date: March 26, 2020
    Inventors: Jack Kuo-Ping Kuo, Sheng-Liang Pan, Chia-Yang Hung, Jyu-Horng Shieh, Shu-Huei Suen, Syun-Ming Jang
  • Patent number: 10553718
    Abstract: A device structure includes: a core structure formed on a support, and a shell material formed on the core structure and surrounding at least part of the core structure. The shell material is associated with a first bandgap; the core structure is associated with a second bandgap; and the first bandgap is smaller than the second bandgap. The shell material and the core structure are configured to form a quantum-well channel in the shell material.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Carlos H. Diaz, Chun-Hsiung Lin, Huicheng Chang, Syun-Ming Jang, Chien-Hsun Wang, Mao-Lin Huang
  • Publication number: 20200020784
    Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.
    Type: Application
    Filed: September 22, 2019
    Publication date: January 16, 2020
    Inventors: Tsan-Chun Wang, Ziwei Fang, Chii-Horng Li, Tze-Liang Lee, Chao-Cheng Chen, Syun-Ming Jang
  • Publication number: 20200004134
    Abstract: In an embodiment, a photomask includes: a substrate over a first conductive layer, the substrate formed of a low thermal expansion material (LTEM); a second conductive layer over the first conductive layer; a reflective film stack over the substrate; a capping layer over the reflective film stack; an absorption layer over the capping layer; and an antireflection (ARC) layer over the absorption layer, where the ARC layer and the absorption layer have a plurality of openings in a first region exposing the capping layer, where the ARC layer, the absorption layer, the capping layer, and the reflective film stack have a trench in a second region exposing the second conductive layer.
    Type: Application
    Filed: September 11, 2019
    Publication date: January 2, 2020
    Inventors: Shiang-Bau Wang, Syun-Ming Jang
  • Patent number: 10510553
    Abstract: An ashing process and device forms radicals of an ashing gas through a secondary reaction. A plasma is generated from a first gas, which is diffused through a first gas distribution plate (GDP). The plasma is diffused through a second GDP and a second gas is supplied below the second GDP. The first gas reacts with the second gas to energize the second gas. The energized second gas is used in ashing a resist layer from a substrate.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jack Kuo-Ping Kuo, Sheng-Liang Pan, Chia-Yang Hung, Jyu-Horng Shieh, Shu-Huei Suen, Syun-Ming Jang
  • Publication number: 20190371619
    Abstract: An ashing process and device forms radicals of an ashing gas through a secondary reaction. A plasma is generated from a first gas, which is diffused through a first gas distribution plate (GDP). The plasma is diffused through a second GDP and a second gas is supplied below the second GDP. The first gas reacts with the second gas to energize the second gas. The energized second gas is used in ashing a resist layer from a substrate.
    Type: Application
    Filed: May 30, 2018
    Publication date: December 5, 2019
    Inventors: Jack Kuo-Ping Kuo, Sheng-Liang Pan, Chia-Yang Hung, Jyu-Horng Shieh, Shu-Huei Suen, Syun-Ming Jang
  • Patent number: 10490648
    Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsan-Chun Wang, Ziwei Fang, Chii-Horng Li, Tze-Liang Lee, Chao-Cheng Chen, Syun-Ming Jang
  • Patent number: 10481483
    Abstract: In an embodiment, a photomask includes: a substrate over a first conductive layer, the substrate formed of a low thermal expansion material (LTEM); a second conductive layer over the first conductive layer; a reflective film stack over the substrate; a capping layer over the reflective film stack; an absorption layer over the capping layer; and an antireflection (ARC) layer over the absorption layer, where the ARC layer and the absorption layer have a plurality of openings in a first region exposing the capping layer, where the ARC layer, the absorption layer, the capping layer, and the reflective film stack have a trench in a second region exposing the second conductive layer.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiang-Bau Wang, Syun-Ming Jang
  • Publication number: 20190267211
    Abstract: Embodiments described herein relate to plasma processes. A tool includes a pedestal. The pedestal is configured to support a semiconductor substrate. The tool includes a bias source. The bias source is electrically coupled to the pedestal. The bias source is operable to bias the pedestal with a direct current (DC) voltage. The tool includes a plasma generator. The plasma generator is operable to generate a plasma remote from the pedestal. A method for semiconductor processing includes performing a plasma process on a substrate in a tool. The plasma process includes flowing a gas into the tool. The plasma process includes biasing a pedestal that supports the substrate in the tool. The plasma process includes igniting a plasma in the tool using the gas.
    Type: Application
    Filed: November 1, 2018
    Publication date: August 29, 2019
    Inventors: Sheng-Liang Pan, Bing-Hung Chen, Chia-Yang Hung, Jyu-Horng Shieh, Shu-Huei Suen, Syun-Ming Jang, Jack Kuo-Ping Kuo
  • Publication number: 20190245057
    Abstract: An embodiment fin field-effect-transistor (finFET) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of the channel region. The gate oxide includes a thinnest portion having a first thickness and a thickest portion having a second thickness different than the first thickness. A difference between the first thickness and the second thickness is less than a maximum thickness variation, and the maximum thickness variation is in accordance with an operating voltage of the finFET.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 8, 2019
    Inventors: Chia-Cheng Chen, Meng-Shu Lin, Liang-Yin Chen, Xiong-Fei Yu, Syun-Ming Jang, Hui-Cheng Chang
  • Patent number: 10269921
    Abstract: An embodiment fin field-effect-transistor (finFET) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of the channel region. The gate oxide includes a thinnest portion having a first thickness and a thickest portion having a second thickness different than the first thickness. A difference between the first thickness and the second thickness is less than a maximum thickness variation, and the maximum thickness variation is in accordance with an operating voltage of the finFET.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chia-Cheng Chen, Liang-Yin Chen, Xiong-Fei Yu, Syun-Ming Jang, Hui-Cheng Chang, Meng-Shu Lin
  • Patent number: 10262944
    Abstract: An interconnect layer is disposed over a substrate. The interconnect layer includes a plurality of dielectric segments interleaved with a plurality of metal components. A plurality of vias is disposed below, and electrically coupled to, a first group of the metal components. A plurality of dielectric components is disposed underneath a second group of the metal components. The dielectric components interleave with the vias. A conductive liner is disposed below a bottom surface and on sidewalk of the vias. A dielectric barrier layer is disposed below a bottom surface and on sidewalls of the dielectric segments. The dielectric barrier layer and the dielectric segments have different material compositions.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: April 16, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai, Syun-Ming Jang
  • Publication number: 20190088499
    Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.
    Type: Application
    Filed: November 2, 2018
    Publication date: March 21, 2019
    Inventors: Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Tai-Chun Huang, Chunyao Wang, Tze-Liang Lee, Chi On Chui
  • Publication number: 20190004416
    Abstract: In an embodiment, a photomask includes: a substrate over a first conductive layer, the substrate formed of a low thermal expansion material (LTEM); a second conductive layer over the first conductive layer; a reflective film stack over the substrate; a capping layer over the reflective film stack; an absorption layer over the capping layer; and an antireflection (ARC) layer over the absorption layer, where the ARC layer and the absorption layer have a plurality of openings in a first region exposing the capping layer, where the ARC layer, the absorption layer, the capping layer, and the reflective film stack have a trench in a second region exposing the second conductive layer.
    Type: Application
    Filed: November 17, 2017
    Publication date: January 3, 2019
    Inventors: Shiang-Bau Wang, Syun-Ming Jang
  • Patent number: 10163719
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate stack over a substrate. The first gate stack includes a gate electrode, a first hard mask (HM) disposed over the gate electrode, and sidewall spacers along sidewalls of the first gate stack. The method also includes forming a first dielectric layer over the first gate stack, forming a second HM over the first HM and top surfaces of sidewall spacers, forming a second dielectric layer over the second HM and the first dielectric layer and removing the second and first dielectric layers to form a trench to expose a portion of the substrate while the second HM is disposed over the first gate stack.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Ping Liu, Hung-Chang Hsu, Hung-Wen Su, Ming-Hsing Tsai, Rueijer Lin, Sheng-Hsuan Lin, Syun-Ming Jang, Ya-Lien Lee, Yen-Shou Kao
  • Publication number: 20180350984
    Abstract: In a method of manufacturing a semiconductor device, a support layer is formed over a substrate. A patterned semiconductor layer made of a first semiconductor material is formed over the support layer. A part of the support layer under a part of the semiconductor layer is removed, thereby forming a semiconductor wire. A semiconductor shell layer made of a second semiconductor material different from the first semiconductor material is formed around the semiconductor wire.
    Type: Application
    Filed: July 30, 2018
    Publication date: December 6, 2018
    Inventors: Carlos H. DIAZ, Chun-Hsiung LIN, Huicheng CHANG, Syun-Ming JANG, Chien-Hsun WANG, Mao-Lin HUANG