Patents by Inventor Syun-Ming Jang

Syun-Ming Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Lithography mask and method
    Patent number: 10481483
    Abstract: In an embodiment, a photomask includes: a substrate over a first conductive layer, the substrate formed of a low thermal expansion material (LTEM); a second conductive layer over the first conductive layer; a reflective film stack over the substrate; a capping layer over the reflective film stack; an absorption layer over the capping layer; and an antireflection (ARC) layer over the absorption layer, where the ARC layer and the absorption layer have a plurality of openings in a first region exposing the capping layer, where the ARC layer, the absorption layer, the capping layer, and the reflective film stack have a trench in a second region exposing the second conductive layer.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiang-Bau Wang, Syun-Ming Jang
  • DC Bias in Plasma Process
    Publication number: 20190267211
    Abstract: Embodiments described herein relate to plasma processes. A tool includes a pedestal. The pedestal is configured to support a semiconductor substrate. The tool includes a bias source. The bias source is electrically coupled to the pedestal. The bias source is operable to bias the pedestal with a direct current (DC) voltage. The tool includes a plasma generator. The plasma generator is operable to generate a plasma remote from the pedestal. A method for semiconductor processing includes performing a plasma process on a substrate in a tool. The plasma process includes flowing a gas into the tool. The plasma process includes biasing a pedestal that supports the substrate in the tool. The plasma process includes igniting a plasma in the tool using the gas.
    Type: Application
    Filed: November 1, 2018
    Publication date: August 29, 2019
    Inventors: Sheng-Liang Pan, Bing-Hung Chen, Chia-Yang Hung, Jyu-Horng Shieh, Shu-Huei Suen, Syun-Ming Jang, Jack Kuo-Ping Kuo
  • Fin Field Effect Transistors having Conformal Oxide Layers and Methods of Forming Same
    Publication number: 20190245057
    Abstract: An embodiment fin field-effect-transistor (finFET) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of the channel region. The gate oxide includes a thinnest portion having a first thickness and a thickest portion having a second thickness different than the first thickness. A difference between the first thickness and the second thickness is less than a maximum thickness variation, and the maximum thickness variation is in accordance with an operating voltage of the finFET.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 8, 2019
    Inventors: Chia-Cheng Chen, Meng-Shu Lin, Liang-Yin Chen, Xiong-Fei Yu, Syun-Ming Jang, Hui-Cheng Chang
  • Fin field effect transistors having conformal oxide layers and methods of forming same
    Patent number: 10269921
    Abstract: An embodiment fin field-effect-transistor (finFET) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of the channel region. The gate oxide includes a thinnest portion having a first thickness and a thickest portion having a second thickness different than the first thickness. A difference between the first thickness and the second thickness is less than a maximum thickness variation, and the maximum thickness variation is in accordance with an operating voltage of the finFET.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chia-Cheng Chen, Liang-Yin Chen, Xiong-Fei Yu, Syun-Ming Jang, Hui-Cheng Chang, Meng-Shu Lin
  • Semiconductor device having interconnect layer that includes dielectric segments interleaved with metal components
    Patent number: 10262944
    Abstract: An interconnect layer is disposed over a substrate. The interconnect layer includes a plurality of dielectric segments interleaved with a plurality of metal components. A plurality of vias is disposed below, and electrically coupled to, a first group of the metal components. A plurality of dielectric components is disposed underneath a second group of the metal components. The dielectric components interleave with the vias. A conductive liner is disposed below a bottom surface and on sidewalk of the vias. A dielectric barrier layer is disposed below a bottom surface and on sidewalls of the dielectric segments. The dielectric barrier layer and the dielectric segments have different material compositions.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: April 16, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai, Syun-Ming Jang
  • Semiconductor Device and Method
    Publication number: 20190088499
    Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.
    Type: Application
    Filed: November 2, 2018
    Publication date: March 21, 2019
    Inventors: Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Tai-Chun Huang, Chunyao Wang, Tze-Liang Lee, Chi On Chui
  • Lithography Mask and Method
    Publication number: 20190004416
    Abstract: In an embodiment, a photomask includes: a substrate over a first conductive layer, the substrate formed of a low thermal expansion material (LTEM); a second conductive layer over the first conductive layer; a reflective film stack over the substrate; a capping layer over the reflective film stack; an absorption layer over the capping layer; and an antireflection (ARC) layer over the absorption layer, where the ARC layer and the absorption layer have a plurality of openings in a first region exposing the capping layer, where the ARC layer, the absorption layer, the capping layer, and the reflective film stack have a trench in a second region exposing the second conductive layer.
    Type: Application
    Filed: November 17, 2017
    Publication date: January 3, 2019
    Inventors: Shiang-Bau Wang, Syun-Ming Jang
  • Method of forming self-alignment contact
    Patent number: 10163719
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate stack over a substrate. The first gate stack includes a gate electrode, a first hard mask (HM) disposed over the gate electrode, and sidewall spacers along sidewalls of the first gate stack. The method also includes forming a first dielectric layer over the first gate stack, forming a second HM over the first HM and top surfaces of sidewall spacers, forming a second dielectric layer over the second HM and the first dielectric layer and removing the second and first dielectric layers to form a trench to expose a portion of the substrate while the second HM is disposed over the first gate stack.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Ping Liu, Hung-Chang Hsu, Hung-Wen Su, Ming-Hsing Tsai, Rueijer Lin, Sheng-Hsuan Lin, Syun-Ming Jang, Ya-Lien Lee, Yen-Shou Kao
  • SEMICONDUCTOR DEVICES WITH CORE-SHELL STRUCTURES
    Publication number: 20180350984
    Abstract: In a method of manufacturing a semiconductor device, a support layer is formed over a substrate. A patterned semiconductor layer made of a first semiconductor material is formed over the support layer. A part of the support layer under a part of the semiconductor layer is removed, thereby forming a semiconductor wire. A semiconductor shell layer made of a second semiconductor material different from the first semiconductor material is formed around the semiconductor wire.
    Type: Application
    Filed: July 30, 2018
    Publication date: December 6, 2018
    Inventors: Carlos H. DIAZ, Chun-Hsiung LIN, Huicheng CHANG, Syun-Ming JANG, Chien-Hsun WANG, Mao-Lin HUANG
  • Semiconductor device and method
    Patent number: 10134604
    Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Tai-Chun Huang, Chunyao Wang, Tze-Liang Lee, Chi On Chui
  • SEMICONDUCTOR DEVICE AND METHOD
    Publication number: 20180315618
    Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.
    Type: Application
    Filed: October 5, 2017
    Publication date: November 1, 2018
    Inventors: Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Tai-Chun Huang, Chunyao Wang, Tze-Liang Lee, Chi On Chui
  • SOURCE/DRAIN RECESS IN A SEMICONDUCTOR DEVICE
    Publication number: 20180315855
    Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.
    Type: Application
    Filed: July 9, 2018
    Publication date: November 1, 2018
    Inventors: Eric PENG, Chao-Cheng CHEN, Chii-Horng LI, Ming-Hua YU, Shih-Hao LO, Syun-Ming JANG, Tze-Liang LEE, Ying Hao HSIEH
  • Bottle-neck recess in a semiconductor device
    Patent number: 10020397
    Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: July 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eric Peng, Chao-Cheng Chen, Chii-Horng Li, Ming-Hua Yu, Shih-Hao Lo, Syun-Ming Jang, Tze-Liang Lee, Ying Hao Hsieh
  • Cleaning method for semiconductor device fabrication
    Patent number: 10005990
    Abstract: A method of cleaning a substrate such as semiconductor substrate for IC fabrication is described that includes cleaning the semiconductor substrate with a first mixture of ozone and one of an acid and a base, followed by a second mixture of ozone and the other one of the acid and the base. The cleaning mixtures may further include de-ionized water. In an embodiment, the mixture is sprayed onto a heated substrate surface. The acid may be HF; the base may be NH4OH.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: June 26, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hsi Yeh, Sung-Hsun Wu, Chao-Cheng Chen, Syun-Ming Jang, Bo-Wei Chou
  • Systems and Methods for Integrated Resputtering in a Physical Vapor Deposition Chamber
    Publication number: 20180158658
    Abstract: Physical vapor deposition systems are disclosed herein. An exemplary physical vapor deposition system includes a target, a collimator, a power source system, and a control system. The power source system is configured to supply power to the collimator and the target. The control system is configured to control the power source system, such that the collimator is bombarded with noble gas ions during a sputtering process and the target is bombarded with metal ions during a re-sputtering process, wherein the collimator functions as a sputtering target during the sputtering process and as the collimator during the re-sputtering process.
    Type: Application
    Filed: January 30, 2018
    Publication date: June 7, 2018
    Inventors: Shing-Chyang Pan, Ching-Hua Hsieh, Ming-Hsing Tsai, Syun-Ming Jang
  • Fin Field Effect Transistors having Conformal Oxide Layers and Methods of Forming Same
    Publication number: 20180145143
    Abstract: An embodiment fin field-effect-transistor (finFET) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of the channel region. The gate oxide includes a thinnest portion having a first thickness and a thickest portion having a second thickness different than the first thickness. A difference between the first thickness and the second thickness is less than a maximum thickness variation, and the maximum thickness variation is in accordance with an operating voltage of the finFET.
    Type: Application
    Filed: November 21, 2016
    Publication date: May 24, 2018
    Inventors: Chia-Cheng Chen, Liang-Yin Chen, Xiong-Fei Yu, Syun-Ming Jang, Hui-Cheng Chang, Meng-Shu Lin
  • Mechanisms of forming damascene interconnect structures
    Patent number: 9953868
    Abstract: A method of forming a conductive structure includes forming a first opening and a second opening in a dielectric layer on a substrate, wherein the first opening is narrower than the second opening. The method further includes depositing a diffusion barrier layer to line the first opening and the second opening. The method further includes forming a metal layer over the diffusion barrier layer to fill at least portions of the first opening and the second opening, wherein a maximum thickness of the metal layer in the first opening is greater than a maximum thickness of the metal layer in the second opening.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: April 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-An Chen, Wen-Jiun Liu, Chun-Chieh Lin, Hung-Wen Su, Ming Hsing Tsai, Syun-Ming Jang
  • Semiconductor device having a fin shell covering a fin core
    Patent number: 9911812
    Abstract: According to an exemplary embodiment, a method of forming a fin structure is provided. The method includes the following operations: etching a first dielectric layer to form at least one recess and a first core portion of a fin core; form an oxide layer as a shallow trench isolation layer in the recess; etching back the oxide layer to expose a portion of the fin core; and forming a fin shell to cover a sidewall of the exposed portion of the fin core.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: March 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chun-Hsiung Lin, Carlos H. Diaz, Hui-Cheng Chang, Syun-Ming Jang, Mao-Lin Huang, Chien-Hsun Wang
  • Systems and methods for integrated resputtering in a physical vapor deposition chamber
    Patent number: 9887072
    Abstract: The present disclosure is directed to a material layer deposition system. The material layer deposition system includes a wafer pedestal configured to support at least one wafer within a confinement shield structure and a target carrier structure positioned above the wafer pedestal at an opposite side of the confinement shield structure. The target carrier structure is configured to support a sputtering target. The material layer deposition system further includes a collimator disposed within the confinement shield structure between the wafer pedestal and the target carrier structure, an electrical power source coupled to the collimator to supply electrical power, and a control system configured to control the electrical power source coupled to the collimator.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shing-Chyang Pan, Ching-Hua Hsieh, Ming-Hsing Tsai, Syun-Ming Jang
  • SEMICONDUCTOR DEVICE WITH PROFILED WORK-FUNCTION METAL GATE ELECTRODE AND METHOD OF MAKING
    Publication number: 20170178973
    Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.
    Type: Application
    Filed: March 6, 2017
    Publication date: June 22, 2017
    Inventors: Da-Yuan Lee, Hung-Chin Chung, Hsien-Ming Lee, Kuan-Ting Liu, Syun-Ming Jang, Weng Chang, Wei-Jen Lo