Abstract: An exemplary shift register (20) includes a plurality of shift register units (200) connected one by one. Each of the shift register units includes a clock signal input terminal (TS), a reverse clock signal input terminal (TSB), a high level signal input terminal (VH), a low level signal input terminal (VL), an output terminal (VOUT), a reverse output terminal (VOUTB), a first input terminal (VIN1), a second input terminal (VIN2), a common node (P), a first switch circuit (31) providing a high level signal to the common node, a second switch circuit (32) providing a low level signal to the common node, a third switch circuit (33) providing a clock signal to the output terminal, a fourth switch circuit (34) providing a low level signal to the output terminal, and an inverter (36) connected between the output terminal and the reverse output terminal.

Abstract: An exemplary shift register (20) includes a plurality of shift register units (200) connected one by one. Each of the shift register units includes a clock signal input terminal (TS), a high level signal input terminal (VH), a low level signal input terminal (VL), an output terminal (VOUT), a reverse output terminal (VOUTB), a first input terminal (VIN1), a second input terminal (VIN2), a first common node (P1), a second common node (P2), a first switch circuit (31), a second switch circuit (32), a third switch circuit (33), a fourth switch circuit (34), a fifth switch circuit (35), a six switch circuit (36), a first inverter (37) connected between the first common node and the second common node, and a second inverter (39) connected between the output terminal and the reverse output terminal.

Abstract: A liquid crystal display (1) includes a liquid crystal panel (10) including pixel units, a digital video card (14), a regulator (12) and a controller (13). The digital video card is configured for sequentially generating video signals. The regulator is configured for generating modulated video signals and generating a black-inserting signal. The controller is configured for receiveing the source video signals, the modulated video signals and the black-inserting signal, and selectively outputting the source video signals, the modulated video signals and the black-inserting signal to the pixel units during each frame.

Abstract: An exemplary shift register (20) includes shift register units (S1˜Sn). The shift register units receive a clock signal and an inverse clock signal and output a plurality of shift register signals in sequence. An output of previous adjacent one of the shift register units is an input of the shift register unit.

Abstract: An exemplary shift register (20) includes a plurality of shift register units (200) connected one by one. Each of the shift register units includes a first switch unit (201), a second switch unit (202), a third switch unit (203), a fourth switch unit (204), and a fifth switch unit (205). A signal input terminal of each shift register unit is coupled to an output terminal of a rear-stage shift register unit. A first clock input terminal receives a first clock signal to turn on/off the first and second switch units. The third switch unit receives a second clock signal. The fourth switch unit pulls up the output voltage of the output terminal according to a controlling signal from the first switch unit. The fifth switch unit pulls down the output voltage of the output terminal according to controlling signals from the second and third switch units.

Abstract: An exemplary shift register (20) includes a plurality of shift register units (200). The shift register units receive a clock signal and an inverse clock signal and output a plurality of shift register signals in sequence. The outputs waveforms of pre-stage shift register unit and the rear-stage shift register unit have no overlapping signals.

Abstract: An exemplary method for driving a typical liquid crystal display (2) with a matrix of pixels (205) includes the steps of: (a) applying video signals with a first polarity pattern to the pixels during a frame period, (b) re-defining the first polarity pattern by sequentially shifting the polarity sequences of one row to an adjacent row within a 2K-by-2K square sub-matrix of the pixels; (c) applying video signals with the re-defined first polarity pattern to the matrix of pixels during next frame period; and (d) repeating steps (b) and (c).

Abstract: An exemplary gamma voltage output circuit (3) has an internal resistor string (31), which has a plurality of resistors and a plurality of nodes; at least one external resistor string (32, 33, 34), which has a plurality of resistors and a plurality of nodes; a plurality of switching circuit (35), each switching circuit having at least one input end (353, 354, 355) and at least one output end (356). The internal and the at least one external resistor strings connect in series between the power source AVDD and ground, respectively. Each node outputs a gamma voltage. The nodes of internal and the at least one external resistor strings respectively are connected to the output end and the input end, the resistors of the internal resistor string parallel connecting to corresponding resistors of the at least one external resistor string through the corresponding switching circuit.

Abstract: An exemplary driving circuit (250) of an LCD (200) includes: gate lines (210) that are parallel to each other and that each extend along a first direction; data lines (202) that are parallel to each other and that each extend along a second direction substantially orthogonal to the first direction; a gate driving circuit (210) connected to the gate lines; a data driving circuit (220) connected to the data lines; and a pre-charging voltage circuit (240). The pre-charging voltage circuit is configured to provide a pre-charging voltage to each of the data lines before the gate driving circuit scans the gate lines.

Abstract: An exemplary clock-pulse generator (60) includes an input port (63), an output port (64), a logic gate (601) having two inputs (602 and 603) and an output (604), an odd number of inverters (606) connected in series between the input port and one of the inputs of the logic gate, an even number of inverters (607 and 608) connected in series between the input port and the other input of the logic gate, and an inverter (605) connected between the output of the logic gate and the output port. The present invention also provides a shift register (6) using the clock-pulse generator.

Abstract: An exemplary liquid crystal display (LCD) (20) includes an LCD panel (24), a timing control circuit (21), a plurality of gate drivers (23) connected to the LCD panel, and a plurality of data drivers (22) connected to the LCD panel. The timing control circuit includes a plurality of reduced swing differential signaling (RSDS) output terminals. Each data driver is electrically connected to a respective RSDS output terminal of the timing control circuit via an independent conducting line.

Abstract: An exemplary liquid crystal display (600) includes a liquid crystal panel, a scanning driving circuit (61), a compensation circuit (68), a control circuit (67), and a signal line driving circuit (62). The liquid crystal panel includes a first substrate, a second substrate opposite to the first substrate, and a liquid crystal layer sandwiched between the first and second substrates. The first substrate includes a plurality of scanning lines (63) that are parallel to each other and that each extend along a first direction, and a plurality of signal lines (64) that are parallel to each other and that each extend along a second direction orthogonal to the first direction. The scanning driving circuit is connected to the scanning lines, and continuously scans the same scanning lines twice in a frame time. The compensation circuit generates first signals. The control circuit generates gradation signals corresponding to the second frame image data.

Abstract: An exemplary liquid crystal display device (1) includes a first substrate (3), a second substrate (2) facing the first substrate, and a liquid crystal layer (4) sandwiched between the first substrate and the second substrate. The first substrate includes a plurality of scan lines (11); a plurality of first and second parallel data lines (12, 22) orthogonal to the scan lines; a plurality of first and second thin film transistors (14, 24), positioned near a crossing of a corresponding scan line and a corresponding first data line, respectively; a plurality of first and second pixel electrodes (15, 25) electrically coupled to the first and second thin film transistors, respectively; a plurality of first and second static display units (19, 29) for providing voltage to the first and second pixel electrodes in a static display mode.

Abstract: An exemplary display system (400) includes an image compensating source disposed in a video source (420), the image compensating source is configured to generate a compensative gray scale voltage signal according to two different images to be displayed by the display system in two sequential frame periods; and an LCD device (410) comprising an LCD panel (40), a gate driving circuit (41), a source driving circuit (42), and a control circuit (47). The LCD panel includes a plurality of pixel units and liquid crystal molecules in the pixel units. The compensating source provides the compensative gray scale voltage signal to the source driving circuit via the control circuit, and the source driving circuit provides corresponding compensative gray scale voltages to the pixel units in order to drive the liquid crystal molecules in the pixel units to twist when the gate driving circuit scans the liquid crystal display panel.

Abstract: An exemplary liquid crystal display device (200) includes: a first substrate, the first substrate including a parallel scan lines (201) and parallel data lines orthogonal to the scan lines (202); pixel electrodes (203); switches (211) each positioned near a crossing of a corresponding scan line and a corresponding data line, a first terminal of each switch being coupled to a scan line, a second terminal of the switch being coupled to a data line, and a third terminal of the switch being coupled to a corresponding pixel electrodes first data memory units (241), each of which outputs voltage signals to a corresponding pixel electrode during a time period in a frame; and second data memory units (242), each of which outputs voltage signals to the pixel electrode during another time period in the same frame.

Abstract: An exemplary shift register system (200) includes a counter (270), a shift register (210), a level shifter (220), and a plurality of switches (231-234). The counter includes a signal receiving pin connecting to a first external circuit, a pulse output pin, and a number of signal output pins. The shift register includes sixty-four register units therein, sixty-four output pins, a start pin connected to the pulse output pin of the counter, a controlling pin connected to the signal receiving pin of the counter. The level shifter includes sixty-four input pins connected to the sixty-four output pins of the shift register, and sixty-four output pins. Each switch includes sixty-four input pins connected to the output pins of the level shift through a bus line (228), sixty-four output pins that are for connection to a second external circuit, and an enabling pin connected to a respective one of the signal output pins of the counter.