Abstract: A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.

Abstract: This application relates to methods and apparatus for refreshing a display device at various frequencies. Specifically, multiple areas of the display device can be refreshed concurrently at different frequencies. In this way, when static content is being displayed in certain areas of the display device, those certain areas can be refreshed at a lower rate than areas displaying dynamic content such as video or animation. By refreshing at lower rates, the energy consumed by the display device and subsystems associated with the display device can be reduced. Additionally, processes for reducing flicker when refreshing the display device at different refresh rates are disclosed herein.

Abstract: This application relates to methods and apparatus for refreshing a display device at various frequencies. Specifically, multiple areas of the display device can be refreshed concurrently at different frequencies. In this way, when static content is being displayed in certain areas of the display device, those certain areas can be refreshed at a lower rate than areas displaying dynamic content such as video or animation. By refreshing at lower rates, the energy consumed by the display device and subsystems associated with the display device can be reduced. Additionally, processes for reducing flicker when refreshing the display device at different refresh rates are disclosed herein.

Abstract: A touch screen. In some examples, the touch screen can comprise a first element coupled to a first sense connection, and a second element coupled to a second sense connection. In some examples, the first and second sense connections can be configured such that a load presented by the first sense connection and the first element is substantially equal to a load presented by the second sense connection and the second element. In some examples, the first and second sense connections can comprise detour routing configured such that a resistance of the first sense connection is substantially equal to a resistance of the second sense connection. In some examples, the first and second sense connections can be coupled to dummy routing configured such that a first capacitance presented by the first sense connection is substantially equal to a second capacitance presented by the second sense connection.

Abstract: Gate line driver circuitry applies an output pulse to each of several gate lines for a display element array. The circuitry has a number of gate drivers each being coupled to drive a respective one of the gate lines. Each of the gate drivers has an output stage in which a high side transistor and a low side transistor are coupled to drive the respective gate line, responsive to at least one clock signal. A pull down transistor is coupled to discharge a control electrode of the output stage. A control circuit having a cascode amplifier is coupled to drive the pull down transistor as a function of a) at least one clock signal and b) feedback from the control electrode. Other embodiments are also described and claimed.

Abstract: A touch screen display may include gate line driver circuitry coupled to a display pixel array. The display may be provided with intra-frame pausing (IFP) capabilities, where touch or other operations may be performed during one or more intra-frame blanking intervals. In one suitable arrangement, a gate driver circuit may include multiple gate line driver segments each of which is activated by a separate gate start pulse. Each gate start pulse may only be released at the end of an IFP interval. In another suitable arrangement, dummy gate driver units may be interposed among active gate driver units. Gate output signals may propagate through the dummy gate driver units during the IFP internal. In another suitable arrangement, each active gate driver unit may be provided with a buffer portion that protects at least some transistor in the gate driver unit from undesired stress.

Abstract: In accordance with some embodiments, a wafer taping device is provided. The wafer taping device includes a tape delivering along a first direction. The wafer taping device also includes a wafer mount unit disposed below the tape. The wafer mount unit has an upper surface for supporting a wafer and having a notch for allowing a cut mark of the wafer to align with it. The notch is staggered with a second direction in the upper surface, and the second direction is substantially perpendicular to the first direction. In addition, the wafer taping device includes a laminating roller disposed above the wafer mount unit and having a long axis elongated in the second direction. The laminating roller is configured to reciprocate along the first direction for pressing the tape to the wafer.

Abstract: A touch screen display may include gate line driver circuitry coupled to a display pixel array. The display may be provided with intra-frame pausing, (IFP) capabilities, where touch or other operations may be performed during one or more intra-frame blanking intervals. In one suitable arrangement, a gate driver circuit may include multiple gate line driver segments each of which is activated by a separate gate start pulse. Each gate start pulse may only be released at the end of an IFP interval. In another suitable arrangement, dummy gate driver units may be interposed among active gate driver units. Gate output signals may propagate through the dummy gate driver units during the IFP internal. In another suitable arrangement, each active gate driver unit may be provided with a buffer portion that protects at least some transistor in the gate driver unit from undesired stress.

Abstract: A container system including cabinets, a main control unit connected to the cabinets and a heat dissipation zone is mentioned. The cabinet includes a plurality of serving zones each of which further includes a master server and at least one slave server. The heat dissipation zone is disposed at a side of the serving zone and coupled to the main control unit. Each slave server is coupled to the master server. The slave server includes at least one temperature sensor, and the temperature sensor is used for outputting temperature information to the master server when receiving the temperature demand. The master server collects the temperature information transmitted by each slave server. The master server forwards the temperature information to the main control unit. The main control unit drives the heat dissipation zone to dissipate heat of the serving zone according to the temperature information.

Abstract: An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure.

Abstract: An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure.

Abstract: A display may include one or more display pixels in an array of pixels. A display pixel may include a storage capacitor chat stores a pixel data signal. The storage capacitor may be formed from a pixel electrode structure, a capacitor electrode structure, and a common electrode structure that is interposed between the pixel electrode structure and capacitor electrode structures. Each electrode structure may be formed from transparent conductive materials deposited on respective display layers. The pixel electrode structure and capacitor electrode structure may be electrically coupled by a conductive via structure that extends through the display layers without contacting the common electrode structure. The conductive via structure may contact underlying transistor structures such as a source-drain structure.

Abstract: A container system and a monitoring method for the container system are provided. The container system includes a plurality of servers and a master server node. The servers are arranged in N areas. The master server node is coupled to the servers. The master server node selects one of a plurality of servers in an ith area to be a main node of the ith area. The main node collects temperature information of the servers in the ith area to transmit highest temperature information to the master server node. When the master server node cannot connect to the main node, the master server node selects one of other servers connected to the master server node in the ith area to be a replacing node, and adjusts the replacing node to be the main node of the ith area to collect the temperature information in the ith area continuously.

Abstract: A method for obtaining an external IP address and its network protocol system are provided. A rack system of the network protocol system comprises a rack management controller (RMC), a power distribution unit and at least one node server. When a Dynamic Host Configuration Protocol (DHCP) service is lost in the rack system, a jumper of the rack management controller is detected to obtain an identification code. Then, a first temporary IP address of the rack management controller is obtained based on the identification code and a first table, and a first command package is sent to the power distribution unit by the rack management controller. After the first command package is received by the power distribution unit, an IP assign service is activated to set a second temporary IP address of the node server so that the node server can still communicate with the system management terminal.

Abstract: A storage device includes a plurality of hard disk device sets, a plurality of voltage adjustment units, an information collection unit and a control unit. The hard disk device sets access data respectively to generate corresponding access messages. Each of the hard disk device sets includes at least two hard disk devices. The voltage adjustment units determine whether to provide a plurality of duty voltages to the hard disk device sets, according to a plurality of control signals. The information collection unit receives the access messages generated by the hard disk device sets, and outputs the access messages according to a read command. The control unit generates the read command to receive the access messages, acquires the usage states of the hard disk device sets according to an algorithm and the access messages, and generates the control signals according to the usage states of the hard disk device sets.

Abstract: A display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor layer. Column spacers may be formed on the color filter layer to maintain a desired gap between the color filter and thin-film transistor layers. Support pads may be used to support the column spacers. Different column spacers may be located at different portions of the support pads to allow the support pad size to be reduced while ensuring adequate support. Lateral movement blocking structures such as circular rings may be used to prevent column spacer lateral movement. Subspacers located over pads may be used to create friction that retards lateral movement. Lateral movement may also be retarded by receiving column spacers in trenches or other recesses formed on a thin-film transistor layer.

Abstract: An electronic device may have a display such as a liquid crystal display. The display may have a color filter layer and a thin-film transistor (TFT) layer. An active portion of the display may contain an array of display pixels that are controlled by control signals that are provided over intersecting gate lines and data lines. In an inactive portion of the display, display driver circuitry may be used to provide data signals for the data lines. Each display pixel may be coupled to a corresponding gate line, data line, and may share a common electrode. Changes in the data signals may be coupled onto the common electrode to cause voltage rippling. Compensation circuitry may be coupled to the common electrode via an AC or a DC coupling connection to help reduce the voltage rippling.

Abstract: An electronic device may have a display such as a liquid crystal display. The display may have a color filter layer and a thin-film transistor layer. An opaque masking layer may be formed on the color filter layer. An active portion of the display may contain an array of display pixels that are controlled by control signals that are provided over intersecting gate lines and data lines. In an inactive portion of the display, gate driver circuits may be used to generate gate line signals for the gate lines. Portions of the gate lines in the gate driver circuitry, power supply lines, and common electrode lines may be formed on the thin-film-transistor layer. These lines may be electromagnetically shielded using indium tin oxide shielding layers to prevent electric fields from inducing charge in the opaque masking layer and thereby causing color artifacts.

Abstract: An electronic display for providing a visual or video output for an electronic device. The electronic device includes a transistor layer configured to activate a first pixel row and a second pixel row. For each pixel in the first pixel row and the second pixel row, the transistor layer includes a switch transistor, a pixel electrode, and a common electrode. The electronic device further includes a pixel controller for selectively activating each pixel. The pixel controller includes a first gate line, a first drive line, and a second drive line. During operation, the first gate line provides a charge to the pixel electrode for a first pixel in the first pixel row and for a second pixel in the second pixel row, and the first drive line activates the switch transistor for the first pixel, and the second drive line activates the switch transistor for the second pixel.

Abstract: Gate line driver circuitry applies an output pulse to each of several gate lines for a display element array. The circuitry has a number of gate drivers each being coupled to drive a respective one of the gate lines. Each of the gate drivers has an output stage in which a high side transistor and a low side transistor are coupled to drive the respective gate line, responsive to at least one clock signal. A pull down transistor is coupled to discharge a control electrode of the output stage. A control circuit having a cascode amplifier is coupled to drive the pull down transistor as a function of a) at least one clock signal and b) feedback from the control electrode. Other embodiments are also described and claimed.