Patents by Inventor Szu-Lin Cheng

Szu-Lin Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190312158
    Abstract: A photo-detecting apparatus includes an absorption layer configured to absorb photons and to generate photo-carriers from the absorbed photons, wherein the absorption layer includes germanium. A carrier guiding unit is electrically coupled to the absorption layer, wherein the carrier guiding unit includes a first switch including a first gate terminal.
    Type: Application
    Filed: April 8, 2019
    Publication date: October 10, 2019
    Inventors: Chien-Yu Chen, Yun-Chung Nah, Szu-Lin Cheng, Ming-Jay Yang, Han-Din Liu, Che-Fu Liang
  • Patent number: 10418407
    Abstract: A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: September 17, 2019
    Assignee: Artilux, Inc.
    Inventors: Yun-Chung Na, Che-Fu Liang, Shu-Lu Chen, Szu-Lin Cheng, Han-Din Liu, Chien-Lung Chen, Yuan-Fu Lyu, Chieh-Ting Lin, Bo-Jiun Chen, Hui-Wen Chen, Shu-Wei Chu, Chung-Chih Lin, Kuan-Chen Chu
  • Patent number: 10403550
    Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: September 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Li Chiang, Chao-Ching Cheng, Chih-Liang Chen, Tzu-Chiang Chen, Ta-Pen Guo, Yu-Lin Yang, I-Sheng Chen, Szu-Wei Huang
  • Publication number: 20190267498
    Abstract: A photo-detecting apparatus includes a semiconductor substrate. A first germanium-based light absorption material is supported by the semiconductor substrate and configured to absorb a first optical signal having a first wavelength greater than 800 nm. A first metal line is electrically coupled to a first region of the first germanium-based light absorption material. A second metal line is electrically coupled to a second region of the first germanium-based light absorption material. The first region is un-doped or doped with a first type of dopants. The second region is doped with a second type of dopants. The first metal line is configured to control an amount of a first type of photo-generated carriers generated inside the first germanium-based light absorption material to be collected by the second region.
    Type: Application
    Filed: February 22, 2019
    Publication date: August 29, 2019
    Inventors: Szu-Lin Cheng, Chien-Yu Chen, Shu-Lin Chen, Yun-Chung Na, Ming-Jay Yang, Han-Din Liu, Che-Fu Liang
  • Publication number: 20190140132
    Abstract: Structures and techniques introduced here enable the design and fabrication of photodetectors (PDs) and/or other electronic circuits using typical semiconductor device manufacturing technologies meanwhile reducing the adverse impacts on PDs' performance. Examples of the various structures and techniques introduced here include, but not limited to, a pre-PD homogeneous wafer bonding technique, a pre-PD heterogeneous wafer bonding technique, a post-PD wafer bonding technique, their combinations, and a number of mirror equipped PD structures. With the introduced structures and techniques, it is possible to implement PDs using typical direct growth material epitaxy technology while reducing the adverse impact of the defect layer at the material interface caused by lattice mismatch.
    Type: Application
    Filed: June 1, 2018
    Publication date: May 9, 2019
    Inventors: Szu-Lin Cheng, Han-Din Liu, Shu-Lu Chen, Yun-Chung Na, Hui-Wen Chen
  • Publication number: 20190140133
    Abstract: Structures and techniques introduced here enable the design and fabrication of photodetectors (PDs) and/or other electronic circuits using typical semiconductor device manufacturing technologies meanwhile reducing the adverse impacts on PDs' performance. Examples of the various structures and techniques introduced here include, but not limited to, a pre-PD homogeneous wafer bonding technique, a pre-PD heterogeneous wafer bonding technique, a post-PD wafer bonding technique, their combinations, and a number of mirror equipped PD structures. With the introduced structures and techniques, it is possible to implement PDs using typical direct growth material epitaxy technology while reducing the adverse impact of the defect layer at the material interface caused by lattice mismatch.
    Type: Application
    Filed: December 13, 2018
    Publication date: May 9, 2019
    Inventors: Chien-Yu Chen, Szu-Lin Cheng, Chieh-Ting Lin, Yu-Hsuan Liu, Ming-Jay Yang, Shu-Lu Chen, Tsung-Ting Wu, Chia-Peng Lin
  • Patent number: 10269862
    Abstract: An optical sensor including a first material layer comprising at least a first material; a second material layer comprising at least a second material that is different from the first material, where a material bandgap of the first material is larger than a material bandgap of the second material; and a graded material layer arranged between the first material layer and the second material layer, the graded material layer comprising an alloy of at least the first material and the second material having compositions of the second material that vary along a direction that is from the first material to the second material.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: April 23, 2019
    Assignee: Artilux Corporation
    Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen
  • Patent number: 10269838
    Abstract: A method for fabricating an image sensor array having a first group of photodiodes for detecting light at visible wavelengths a second group of photodiodes for detecting light at infrared or near-infrared wavelengths, the method including forming a germanium-silicon layer for the second group of photodiodes on a first semiconductor donor wafer; defining a first interconnect layer on the germanium-silicon layer; defining integrated circuitry for controlling pixels of the image sensor array on a semiconductor carrier wafer; defining a second interconnect layer on the semiconductor carrier wafer; bonding the first interconnect layer with the second interconnect layer; defining the pixels of an image sensor array on a second semiconductor donor wafer; defining a third interconnect layer on the image sensor array; and bonding the third interconnect layer with the germanium-silicon layer.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: April 23, 2019
    Assignee: Artilux Corporation
    Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen, Che-Fu Liang
  • Patent number: 10256264
    Abstract: An image sensor array including a carrier substrate; a first group of photodiodes coupled to the carrier substrate, where the first group of photodiodes include a first photodiode, and where the first photodiode includes a semiconductor layer configured to absorb photons at visible wavelengths and to generate photo-carriers from the absorbed photons; and a second group of photodiodes coupled to the carrier substrate, where the second group of photodiodes include a second photodiode, and where the second photodiode includes a germanium-silicon region fabricated on the semiconductor layer, the germanium-silicon region configured to absorb photons at infrared or near-infrared wavelengths and to generate photo-carriers from the absorbed photons.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: April 9, 2019
    Assignee: Artilux Corporation
    Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen, Che-Fu Liang
  • Publication number: 20190103435
    Abstract: An optical sensor including a semiconductor substrate; a first light absorption region formed in the semiconductor substrate, the first light absorption region configured to absorb photons at a first wavelength range and to generate photo-carriers from the absorbed photons; a second light absorption region formed on the first light absorption region, the second light absorption region configured to absorb photons at a second wavelength range and to generate photo-carriers from the absorbed photons; and a sensor control signal coupled to the second light absorption region, the sensor control signal configured to provide at least a first control level and a second control level.
    Type: Application
    Filed: December 3, 2018
    Publication date: April 4, 2019
    Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen, Che-Fu Liang
  • Publication number: 20190051765
    Abstract: Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.
    Type: Application
    Filed: October 10, 2018
    Publication date: February 14, 2019
    Inventors: Szu-Lin Cheng, Shu-Lu Chen
  • Patent number: 10170608
    Abstract: A semiconductor device includes a first source/drain region a second source/drain region, and a gate region interposed between the first and second source/drain regions. At least one nanowire has a first end anchored to the first source/drain region and an opposing second end anchored to the second source/drain region such that the nanowire is suspended above the wafer in the gate region. At least one gate electrode is in the gate region. The gate electrode contacts an entire surface of the nanowire to define a gate-all-around configuration. At least one pair of oxidized spacers surrounds the at least one gate electrode to electrically isolate the at least one gate electrode from the first and second source/drain regions.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Szu-Lin Cheng, Michael A. Guillorn, Gen P. Lauer, Isaac Lauer
  • Patent number: 10170609
    Abstract: A semiconductor device includes a first source/drain region a second source/drain region, and a gate region interposed between the first and second source/drain regions. At least one nanowire has a first end anchored to the first source/drain region and an opposing second end anchored to the second source/drain region such that the nanowire is suspended above the wafer in the gate region. At least one gate electrode is in the gate region. The gate electrode contacts an entire surface of the nanowire to define a gate-all-around configuration. At least one pair of oxidized spacers surrounds the at least one gate electrode to electrically isolate the at least one gate electrode from the first and second source/drain regions.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Szu-Lin Cheng, Michael A. Guillorn, Gen P. Lauer, Isaac Lauer
  • Patent number: 10157954
    Abstract: An optical sensor including a semiconductor substrate; a first light absorption region formed in the semiconductor substrate, the first light absorption region configured to absorb photons at a first wavelength range and to generate photo-carriers from the absorbed photons; a second light absorption region formed on the first light absorption region, the second light absorption region configured to absorb photons at a second wavelength range and to generate photo-carriers from the absorbed photons; and a sensor control signal coupled to the second light absorption region, the sensor control signal configured to provide at least a first control level and a second control level.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: December 18, 2018
    Assignee: Artilux Corporation
    Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen, Che-Fu Liang
  • Patent number: 10128303
    Abstract: A light absorption apparatus includes a substrate, a light absorption layer above the substrate on a first selected area, a silicon layer above the light absorption layer, a spacer surrounding at least part of the sidewall of the light absorption layer, an isolation layer surrounding at least part of the spacer, wherein the light absorption apparatus can achieve high bandwidth and low dark current.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: November 13, 2018
    Assignee: Artilux Inc.
    Inventors: Szu-Lin Cheng, Han-Din Liu, Shu-Lu Chen
  • Publication number: 20180308882
    Abstract: A light absorption apparatus includes a substrate, a light absorption layer above the substrate on a first selected area, a silicon layer above the light absorption layer, a spacer surrounding at least part of the sidewall of the light absorption layer, an isolation layer surrounding at least part of the spacer, wherein the light absorption apparatus can achieve high bandwidth and low dark current.
    Type: Application
    Filed: June 29, 2018
    Publication date: October 25, 2018
    Inventors: Szu-Lin CHENG, Shu-Lu CHEN
  • Publication number: 20180269239
    Abstract: A method for fabricating an image sensor array having a first group of photodiodes for detecting light at visible wavelengths a second group of photodiodes for detecting light at infrared or near-infrared wavelengths, the method including forming a germanium-silicon layer for the second group of photodiodes on a first semiconductor donor wafer; defining a first interconnect layer on the germanium-silicon layer; defining integrated circuitry for controlling pixels of the image sensor array on a semiconductor carrier wafer; defining a second interconnect layer on the semiconductor carrier wafer; bonding the first interconnect layer with the second interconnect layer; defining the pixels of an image sensor array on a second semiconductor donor wafer; defining a third interconnect layer on the image sensor array; and bonding the third interconnect layer with the germanium-silicon layer.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen, Che-Fu Liang
  • Publication number: 20180261645
    Abstract: A method for fabricating an optical sensor includes: forming, over a substrate, a first material layer comprising a first alloy of germanium and silicon having a first germanium composition; forming, over the first material layer, a graded material layer comprising germanium and silicon; and forming, over the graded material layer, a second material layer comprising a second alloy of germanium and silicon having a second germanium composition. The first germanium composition is lower than the second germanium composition and a germanium composition of the graded material layer is between the first germanium composition and the second germanium composition and varies along a direction perpendicular to the substrate.
    Type: Application
    Filed: May 16, 2018
    Publication date: September 13, 2018
    Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen
  • Patent number: 10074677
    Abstract: A light absorption apparatus includes a substrate, a light absorption layer above the substrate on a first selected area, a silicon layer above the light absorption layer, a spacer surrounding at least part of the sidewall of the light absorption layer, an isolation layer surrounding at least part of the spacer, wherein the light absorption apparatus can achieve high bandwidth and low dark current.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: September 11, 2018
    Assignee: Artilux Inc.
    Inventors: Szu-Lin Cheng, Shu-Lu Chen
  • Publication number: 20180247968
    Abstract: A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.
    Type: Application
    Filed: April 3, 2018
    Publication date: August 30, 2018
    Inventors: Yun-Chung Na, Che-Fu Liang, Shu-Lu Chen, Szu-Lin Cheng, Han-Din Liu, Chien-Lung Chen, Yuan-Fu Lyu, Chieh-Ting Lin, Bo-Jiun Chen, Hui-Wen Chen, Shu-Wei Chu, Chung-Chih Lin, Kuan-Chen Chu