Patents by Inventor Szu-Wei Huang
Szu-Wei Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10804268Abstract: A semiconductor device includes a substrate, a first source/drain structure, a vertical channel layer, a gate structure, a second source/drain structure and a body epitaxial layer. The first source/drain structure is over the substrate. The vertical channel layer is over the first source/drain structure. The gate structure is on a first sidewall of the vertical channel layer. The second source/drain structure is over the vertical channel layer. The body epitaxial layer is on a second sidewall of the vertical channel layer. The body epitaxial layer and the vertical channel layer are of opposite conductivity types, and the body epitaxial layer is separated from the gate structure.Type: GrantFiled: April 22, 2019Date of Patent: October 13, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Li Chiang, Szu-Wei Huang, Chih-Chieh Yeh, Yee-Chia Yeo
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Patent number: 10699956Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.Type: GrantFiled: November 1, 2017Date of Patent: June 30, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Li Chiang, Chao-Ching Cheng, Chih-Liang Chen, Tzu-Chiang Chen, Ta-Pen Guo, Yu-Lin Yang, I-Sheng Chen, Szu-Wei Huang
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Publication number: 20200075427Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a number of first semiconductor wires over a semiconductor substrate, and the first semiconductor wires are vertically spaced apart from each other. The semiconductor device structure includes a first gate stack partially wrapping the first semiconductor wires, and a spacer element adjacent to the first gate stack. Each of the first semiconductor wires has a first portion directly below the spacer element and a second portion directly below the first gate stack, the first portion has a first width, the second portion has a second width, and the first width is greater than the second width.Type: ApplicationFiled: November 7, 2019Publication date: March 5, 2020Inventors: Hung-Li CHIANG, I-Sheng CHEN, Tzu-Chiang CHEN, Tung-Ying LEE, Szu-Wei HUANG, Huan-Sheng WEI
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Publication number: 20200052133Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a core region, and one or more shell regions. The core region has an approximately square-shape cross section and a first shell of the one or more shells forms a first shell region of an approximately rhombus-shape cross section around the core region and is connected to an adjacent first shell region corresponding to a neighboring semiconductor wire.Type: ApplicationFiled: October 18, 2019Publication date: February 13, 2020Inventors: I-Sheng CHEN, Szu-Wei HUANG, Hung-Li CHIANG, Cheng-Hsien WU, Chih Chieh YEH
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Publication number: 20200035562Abstract: A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.Type: ApplicationFiled: October 7, 2019Publication date: January 30, 2020Inventors: Hung-Li Chiang, Szu-Wei Huang, Huan-Sheng Wei, Jon-Hsu Ho, Chih Chieh Yeh, Wen-Hsing Hsieh, Chung-Cheng Wu, Yee-Chia Yeo
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Patent number: 10522694Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a core region, and one or more shell regions. The core region has an approximately square-shape cross section and a first shell of the one or more shells forms a first shell region of an approximately rhombus-shape cross section around the core region and is connected to an adjacent first shell region corresponding to a neighboring semiconductor wire.Type: GrantFiled: September 28, 2017Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: I-Sheng Chen, Szu-Wei Huang, Hung-Li Chiang, Cheng-Hsien Wu, Chih Chieh Yeh
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Publication number: 20190393102Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.Type: ApplicationFiled: August 29, 2019Publication date: December 26, 2019Inventors: Hung-Li CHIANG, Chao-Ching CHENG, Chih-Liang CHEN, Tzu-Chiang CHEN, Ta-Pen GUO, Yu-Lin YANG, I-Sheng CHEN, Szu-Wei HUANG
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Patent number: 10438851Abstract: A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.Type: GrantFiled: July 30, 2018Date of Patent: October 8, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Li Chiang, Szu-Wei Huang, Huan-Sheng Wei, Jon-Hsu Ho, Chih Chieh Yeh, Wen-Hsing Hsieh, Chung-Cheng Wu, Yee-Chia Yeo
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Patent number: 10403550Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.Type: GrantFiled: January 31, 2018Date of Patent: September 3, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Li Chiang, Chao-Ching Cheng, Chih-Liang Chen, Tzu-Chiang Chen, Ta-Pen Guo, Yu-Lin Yang, I-Sheng Chen, Szu-Wei Huang
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Publication number: 20190267292Abstract: Semiconductor device structures are provided. The semiconductor device structure includes first semiconductor wires over a semiconductor substrate. The first semiconductor wires are vertically spaced apart from each other. The semiconductor device structure also includes a gate stack surrounding first portions of the first semiconductor wires, and a spacer element surrounding second portions of the first semiconductor wires. The first portions have a first width and the second portions have a second width. In addition, the semiconductor device structure includes a second semiconductor wire between the second portions. The second semiconductor wire has a third width, and the third width is substantially equal to the second width and greater than the first width.Type: ApplicationFiled: May 10, 2019Publication date: August 29, 2019Inventors: Hung-Li Chiang, I-Sheng Chen, Tzu-Chiang Chen, Tung-Ying Lee, Szu-Wei Huang, Huan-Sheng Wei
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Publication number: 20190267376Abstract: A semiconductor device includes a substrate, a first source/drain structure, a vertical channel layer, a gate structure, a second source/drain structure and a body epitaxial layer. The first source/drain structure is over the substrate. The vertical channel layer is over the first source/drain structure. The gate structure is on a first sidewall of the vertical channel layer. The second source/drain structure is over the vertical channel layer. The body epitaxial layer is on a second sidewall of the vertical channel layer. The body epitaxial layer and the vertical channel layer are of opposite conductivity types, and the body epitaxial layer is separated from the gate structure.Type: ApplicationFiled: April 22, 2019Publication date: August 29, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Li CHIANG, Szu-Wei HUANG, Chih-Chieh YEH, Yee-Chia YEO
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Patent number: 10290546Abstract: A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.Type: GrantFiled: August 2, 2017Date of Patent: May 14, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Li Chiang, Szu-Wei Huang, Huan-Sheng Wei, Jon-Hsu Ho, Chih Chieh Yeh, Wen-Hsing Hsieh, Chung-Cheng Wu, Yee-Chia Yeo
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Patent number: 10290548Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a first semiconductor wire over a semiconductor substrate. The first semiconductor wire has a first width and a first thickness. The semiconductor device structure also includes a first gate stack surrounding the first semiconductor wire. The semiconductor device structure further includes a second semiconductor wire over the semiconductor substrate. The first semiconductor wire and the second semiconductor wire include different materials. The second semiconductor wire has a second width and a second thickness. The first width is greater than the second width. The first thickness is less than the second thickness. In addition, the semiconductor device structure includes a second gate stack surrounding the second semiconductor wire.Type: GrantFiled: August 31, 2017Date of Patent: May 14, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Li Chiang, I-Sheng Chen, Tzu-Chiang Chen, Tung-Ying Lee, Szu-Wei Huang, Huan-Sheng Wei
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Patent number: 10269800Abstract: A semiconductor device includes a substrate, a well on the substrate and an FFT on the well. The FET includes a first source/drain, a vertical channel layer, a gate structure, a second source/drain and a body structure. The first source/drain is on the well. The vertical channel layer extends form the first source/drain. The first gate structure surrounds a first portion of sidewalls of the vertical channel layer. The second source/drain is on the vertical channel layer. The body structure is in physical contact with the vertical channel layer. The body structure and the vertical channel layer constitute a bipolar device.Type: GrantFiled: May 26, 2017Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Li Chiang, Szu-Wei Huang, Chih-Chieh Yeh, Yee-Chia Yeo
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Publication number: 20190088797Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a core region, and one or more shell regions. The core region has an approximately square-shape cross section and a first shell of the one or more shells forms a first shell region of an approximately rhombus-shape cross section around the core region and is connected to an adjacent first shell region corresponding to a neighboring semiconductor wire.Type: ApplicationFiled: November 20, 2018Publication date: March 21, 2019Inventors: I-Sheng CHEN, Szu-Wei HUANG, Hung-Li CHIANG, Cheng-Hsien WU, Chih Chieh YEH
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Publication number: 20190067113Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.Type: ApplicationFiled: November 1, 2017Publication date: February 28, 2019Inventors: Hung-Li CHIANG, Chao-Ching CHENG, Chih-Liang CHEN, Tzu-Chiang CHEN, Ta-Pen GUO, Yu-Lin YANG, I-Sheng CHEN, Szu-Wei HUANG
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Publication number: 20190067121Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a first semiconductor wire over a semiconductor substrate. The first semiconductor wire has a first width and a first thickness. The semiconductor device structure also includes a first gate stack surrounding the first semiconductor wire. The semiconductor device structure further includes a second semiconductor wire over the semiconductor substrate. The first semiconductor wire and the second semiconductor wire include different materials. The second semiconductor wire has a second width and a second thickness. The first width is greater than the second width. The first thickness is less than the second thickness. In addition, the semiconductor device structure includes a second gate stack surrounding the second semiconductor wire.Type: ApplicationFiled: August 31, 2017Publication date: February 28, 2019Inventors: Hung-Li CHIANG, I-Sheng CHEN, Tzu-Chiang CHEN, Tung-Ying LEE, Szu-Wei HUANG, Huan-Sheng WEI
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Publication number: 20190067125Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.Type: ApplicationFiled: January 31, 2018Publication date: February 28, 2019Inventors: Hung-Li CHIANG, Chao-Ching CHENG, Chih-Liang CHEN, Tzu-Chiang CHEN, Ta-Pen GUO, Yu-Lin YANG, I-Sheng CHEN, Szu-Wei HUANG
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Publication number: 20180342516Abstract: A semiconductor device includes a substrate, a well on the substrate and an FFT on the well. The FET includes a first source/drain, a vertical channel layer, a gate structure, a second source/drain and a body structure. The first source/drain is on the well. The vertical channel layer extends form the first source/drain. The first gate structure surrounds a first portion of sidewalls of the vertical channel layer. The second source/drain is on the vertical channel layer. The body structure is in physical contact with the vertical channel layer. The body structure and the vertical channel layer constitute a bipolar device.Type: ApplicationFiled: May 26, 2017Publication date: November 29, 2018Inventors: Hung-Li CHIANG, Szu-Wei HUANG, Chih-Chieh YEH, Yee-Chia YEO
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Publication number: 20180337094Abstract: A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.Type: ApplicationFiled: July 30, 2018Publication date: November 22, 2018Inventors: Hung-Li Chiang, Szu-Wei Huang, Huan-Sheng Wei, Jon-Hsu Ho, Chih Chieh Yeh, Wen-Hsing Hsieh, Chung-Cheng Wu, Yee-Chia Yeo