Patents by Inventor Ta-Cheng Lien
Ta-Cheng Lien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240369921Abstract: A reticle enclosure includes a base including a first surface, a cover including a second surface and disposed on the base, wherein the base and the cover form an internal space therebetween to include a reticle, and a layer of elastomer or gelatinous material disposed on at least one of the first surface and the second surface, wherein the layer of elastomer or gelatinous material is disposed between the base and the cover and contacts either the base or the cover.Type: ApplicationFiled: July 18, 2024Publication date: November 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Cheng HSU, Ta-Cheng LIEN, Hsin-Chang LEE
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Publication number: 20240369918Abstract: In a method of manufacturing a photo mask, an etching mask layer having circuit patterns is formed over a target layer of the photo mask to be etched. The photo mask includes a backside conductive layer. The target layer is etched by plasma etching, while preventing active species of plasma from attacking the backside conductive layer.Type: ApplicationFiled: July 12, 2024Publication date: November 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Chang LEE, Pei-Cheng HSU, Ta-Cheng LIEN, Tzu Yi WANG
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Patent number: 12135499Abstract: A reticle enclosure includes a base including a first surface, a cover including a second surface and disposed on the base, wherein the base and the cover form an internal space therebetween to include a reticle, and a layer of elastomer or gelatinous material disposed on at least one of the first surface and the second surface, wherein the layer of elastomer or gelatinous material is disposed between the base and the cover and contacts either the base or the cover.Type: GrantFiled: August 30, 2021Date of Patent: November 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pei-Cheng Hsu, Ta-Cheng Lien, Hsin-Chang Lee
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Publication number: 20240345472Abstract: A method for preparing a pellicle assembly includes reducing the thickness of one or more initial membrane(s) to obtain a pellicle membrane. The pellicle membrane is then affixed to a mounting frame to obtain the pellicle assembly. Compressive pressure can be applied to reduce the thickness of the initial membrane(s). Alternatively, the thickness can be reduced by stretching the initial membrane(s) to obtain an extended membrane. A mounting frame is then affixed to a portion of the extended membrane. The mounting frame and the portion of the extended membrane are then separated from the remainder of the extended membrane to obtain the pellicle assembly. The resulting pellicle assemblies include a pellicle membrane that is attached to a mounting frame. The pellicle membrane can be formed from nanotubes and has a combination of high transmittance, low deflection, and small pore size.Type: ApplicationFiled: June 24, 2024Publication date: October 17, 2024Inventors: Hsin-Chang Lee, Pei-Cheng Hsu, Ta-Cheng Lien, Li-Jui Chen, Tsai-Sheng Gau, Chin-Hsiang Lin
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Publication number: 20240337918Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes a base material made of one or more of a Cr based material, an Ir based material, a Pt based material, or Co based material, and further contains one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.Type: ApplicationFiled: June 20, 2024Publication date: October 10, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Yi TSAI, Wei-Che HSIEH, Ta-Cheng LIEN, Hsin-Chang LEE, Ping-Hsun LIN, Hao-Ping CHENG, Ming-Wei CHEN, Szu-Ping TSAI
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Publication number: 20240337917Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes one or more alternating pairs of a first Cr based layer and a second Cr based layer different from the first Cr based layer.Type: ApplicationFiled: June 17, 2024Publication date: October 10, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Cheng HSU, Ching-Huang CHEN, Hung-Yi TSAI, Ming-Wei CHEN, Hsin-Chang LEE, Ta-Cheng LIEN
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Patent number: 12092952Abstract: An extreme ultraviolet mask includes a substrate, a reflective multilayer stack over the substrate, a capping layer over the reflective multilayer stack, a patterned absorber layer over a first portion of the capping layer, and a magnetic layer over a second portion of the capping layer around the first portion.Type: GrantFiled: June 14, 2021Date of Patent: September 17, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kevin Tanady, Pei-Cheng Hsu, Ta-Cheng Lien, Tzu-Yi Wang, Hsin-Chang Lee
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Publication number: 20240302731Abstract: A reflective mask includes a substrate, a reflective multilayer disposed over the substrate, a capping layer disposed over the reflective multilayer, an intermediate layer disposed over the capping layer, an absorber layer disposed over the intermediate layer, and a cover layer disposed over the absorber layer. The intermediate layer includes a material having a lower hydrogen diffusivity than a material of the capping layer.Type: ApplicationFiled: May 8, 2024Publication date: September 12, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Cheng HSU, Ta-Cheng LIEN, Hsin-Chang LEE
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Patent number: 12085843Abstract: In a method of manufacturing a photo mask, an etching mask layer having circuit patterns is formed over a target layer of the photo mask to be etched. The photo mask includes a backside conductive layer. The target layer is etched by plasma etching, while preventing active species of plasma from attacking the backside conductive layer.Type: GrantFiled: July 25, 2023Date of Patent: September 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Chang Lee, Pei-Cheng Hsu, Ta-Cheng Lien, Tzu Yi Wang
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Publication number: 20240264520Abstract: The present disclosure describes a method of patterning a semiconductor wafer using extreme ultraviolet lithography (EUVL). The method includes receiving an EUVL mask that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further includes patterning the absorber layer to form a trench on the EUVL mask, wherein the trench has a first width above a target width. The method further includes treating the EUVL mask with oxygen plasma to reduce the trench to a second width, wherein the second width is below the target width. The method may also include treating the EUVL mask with nitrogen plasma to protect the capping layer, wherein the treating of the EUVL mask with the nitrogen plasma expands the trench to a third width at the target width.Type: ApplicationFiled: April 15, 2024Publication date: August 8, 2024Inventors: Pei-Cheng Hsu, Chun-Fu Yang, Ta-Cheng Lien, Hsin-Chang Lee
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Patent number: 12050399Abstract: A method for preparing a pellicle assembly includes reducing the thickness of one or more initial membrane(s) to obtain a pellicle membrane. The pellicle membrane is then affixed to a mounting frame to obtain the pellicle assembly. Compressive pressure can be applied to reduce the thickness of the initial membrane(s). Alternatively, the thickness can be reduced by stretching the initial membrane(s) to obtain an extended membrane. A mounting frame is then affixed to a portion of the extended membrane. The mounting frame and the portion of the extended membrane are then separated from the remainder of the extended membrane to obtain the pellicle assembly. The resulting pellicle assemblies include a pellicle membrane that is attached to a mounting frame. The pellicle membrane can be formed from nanotubes and has a combination of high transmittance, low deflection, and small pore size.Type: GrantFiled: May 12, 2021Date of Patent: July 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Chang Lee, Pei-Cheng Hsu, Ta-Cheng Lien, Li-Jui Chen, Tsai-Sheng Gau, Chin-Hsiang Lin
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Patent number: 12044959Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes a base material made of one or more of a Cr based material, an Ir based material, a Pt based material, or Co based material, and further contains one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.Type: GrantFiled: February 27, 2023Date of Patent: July 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Yi Tsai, Wei-Che Hsieh, Ta-Cheng Lien, Hsin-Chang Lee, Ping-Hsun Lin, Hao-Ping Cheng, Ming-Wei Chen, Szu-Ping Tsai
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Patent number: 12044960Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes one or more alternating pairs of a first Cr based layer and a second Cr based layer different from the first Cr based layer.Type: GrantFiled: June 26, 2023Date of Patent: July 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pei-Cheng Hsu, Ching-Huang Chen, Hung-Yi Tsai, Ming-Wei Chen, Hsin-Chang Lee, Ta-Cheng Lien
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Patent number: 12019367Abstract: A reflective mask blank includes a substrate, a reflective multilayer (RML) disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer has length or width dimensions smaller than the capping layer, and part of the capping layer is exposed by the absorber layer. The dimension of the absorber layer and the hard mask layer ranges between 146 cm to 148 cm. The dimensions of the substrate, the RML, and the capping layer range between 150 cm to 152 cm.Type: GrantFiled: December 19, 2022Date of Patent: June 25, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Chang Lee, Pei-Cheng Hsu, Ta-Cheng Lien, Wen-Chang Hsueh
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Patent number: 12013630Abstract: A reflective mask includes a substrate, a reflective multilayer disposed over the substrate, a capping layer disposed over the reflective multilayer, an intermediate layer disposed over the capping layer, an absorber layer disposed over the intermediate layer, and a cover layer disposed over the absorber layer. The intermediate layer includes a material having a lower hydrogen diffusivity than a material of the capping layer.Type: GrantFiled: November 21, 2022Date of Patent: June 18, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pei-Cheng Hsu, Ta-Cheng Lien, Hsin-Chang Lee
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Publication number: 20240192581Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a patterned absorber layer on the reflective multilayer stack is provided. The patterned absorber layer includes an alloy comprising tantalum and at least one alloying element. The at least one alloying element includes at least one transition metal element or at least one Group 14 element.Type: ApplicationFiled: December 22, 2023Publication date: June 13, 2024Inventors: Pei-Cheng HSU, Ta-Cheng LIEN, Hsin-Chang LEE
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Patent number: 12001132Abstract: Fabricating a photomask includes forming a protection layer over a substrate. A plurality of multilayers of reflecting films are formed over the protection layer. A capping layer is formed over the plurality of multilayers. An absorption layer is formed over capping layer. A first photoresist layer is formed over portions of absorption layer. Portions of the first photoresist layer and absorption layer are patterned, forming first openings in absorption layer. The first openings expose portions of the capping layer. Remaining portions of first photoresist layer are removed and a second photoresist layer is formed over portions of absorption layer. The second photoresist layer covers at least the first openings. Portions of the absorption layer and capping layer and plurality of multilayer of reflecting films not covered by the second photoresist layer are patterned, forming second openings. The second openings expose portions of protection layer and second photoresist layer is removed.Type: GrantFiled: August 7, 2019Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pei-Cheng Hsu, Ta-Cheng Lien, Ping-Hsun Lin, Shih-Che Wang, Hsin-Chang Lee
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Patent number: 11988953Abstract: A method includes forming a multi-layered reflective layer over a substrate; depositing a metal capping layer over the multi-layered reflective layer; depositing a first metal oxide layer over the metal capping layer; depositing a metal nitride layer over the first metal oxide layer; depositing a second metal oxide layer over the metal nitride layer; forming a plurality of features on the second metal oxide layer and the metal nitride layer.Type: GrantFiled: January 6, 2023Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Cheng Hsu, Ta-Cheng Lien, Hsin-Chang Lee
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Publication number: 20240134268Abstract: A mask for use in a semiconductor lithography process includes a substrate, a mask pattern disposed on the substrate, and a light absorbing border surrounding the mask pattern. The light absorbing border is inset from at least two edges of the substrate to define a peripheral region outside of the light absorbing border. In some designs, a first peripheral region extends from an outer perimeter of the light absorbing border to a first edge of the substrate, and a second peripheral region that extends from the outer perimeter of the light absorbing border to a second edge of the substrate, where the first edge of the substrate and the second edge of the substrate are on opposite sides of the mask pattern.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Inventors: Chien-Cheng Chen, Huan-Ling Lee, Ta-Cheng Lien, Chia-Jen Chen, Hsin-Chang Lee
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Patent number: 11960201Abstract: The present disclosure describes a method of patterning a semiconductor wafer using extreme ultraviolet lithography (EUVL). The method includes receiving an EUVL mask that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further includes patterning the absorber layer to form a trench on the EUVL mask, wherein the trench has a first width above a target width. The method further includes treating the EUVL mask with oxygen plasma to reduce the trench to a second width, wherein the second width is below the target width. The method may also include treating the EUVL mask with nitrogen plasma to protect the capping layer, wherein the treating of the EUVL mask with the nitrogen plasma expands the trench to a third width at the target width.Type: GrantFiled: May 15, 2023Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Cheng Hsu, Chun-Fu Yang, Ta-Cheng Lien, Hsin-Chang Lee