Patents by Inventor Ta-Jen Yu
Ta-Jen Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240332266Abstract: A semiconductor device is provided. The semiconductor device includes a bottom package and a top package. The top package is mounted on the bottom package. At least one portion of the top package protrudes from a sidewall of the bottom package. The semiconductor device further includes a passive device mounted on a protruding region of the portion of the top package.Type: ApplicationFiled: January 5, 2024Publication date: October 3, 2024Inventors: Che-Hung KUO, Ta-Jen YU, Chi-Hung HUANG
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Publication number: 20240274517Abstract: A semiconductor package structure includes a first component, a bonding structure on the first component, a second component connected to the first component, and a copper connector on the second component. The bonding structure includes a copper base on the first component and copper protruding portions on the copper base. The second component is connected to the first component by bonding the copper protruding portions to the copper connector, and the copper protruding portions are in contact with the copper connector.Type: ApplicationFiled: January 22, 2024Publication date: August 15, 2024Inventors: Fa-Chuan CHEN, Ta-Jen YU, Bo-Jiun YANG, Tsung-Yu PAN, Tai-Yu CHEN, Nai-Wei LIU, Shih-Chin LIN, Wen-Sung HSU
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Publication number: 20230422525Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die and a memory die are mounted on a top surface of the bottom substrate in a side-by-side fashion. The logic die may have a thickness not less than 125 micrometers. A connection structure is disposed between the bottom substrate and the top substrate around the logic die and the memory die to electrically connect the bottom substrate with the top substrate. A sealing resin fills in the gap between the bottom substrate and the top substrate and sealing the logic die, the memory die, and the connection structure in the gap.Type: ApplicationFiled: May 31, 2023Publication date: December 28, 2023Applicant: MEDIATEK INC.Inventors: Ta-Jen Yu, Wen-Chin Tsai, Isabella Song, Che-Hung Kuo, Hsing-Chih Liu, Tai-Yu Chen, Shih-Chin Lin, Wen-Sung Hsu
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Patent number: 11854784Abstract: A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.Type: GrantFiled: November 17, 2022Date of Patent: December 26, 2023Assignee: MediaTek Inc.Inventors: Yen-Yao Chi, Nai-Wei Liu, Ta-Jen Yu, Tzu-Hung Lin, Wen-Sung Hsu, Shih-Chin Lin
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Patent number: 11791266Abstract: A semiconductor package structure including a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. A first protective insulating layer covers the first and third surfaces of the semiconductor die. A redistribution layer (RDL) structure is electrically coupled to the semiconductor die and surrounded by the first protective insulating layer on the first surface of the semiconductor die. A first passivation layer covers the first protective insulating layer and the RDL structure. At least one conductive structure passes through the first passivation layer and is electrically coupled to the RDL structure. A method of forming the semiconductor package is also provided.Type: GrantFiled: August 12, 2022Date of Patent: October 17, 2023Assignee: MediaTek Inc.Inventors: Yen-Yao Chi, Nai-Wei Liu, Ta-Jen Yu, Tzu-Hung Lin, Wen-Sung Hsu
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Publication number: 20230307421Abstract: A package-on-package includes a first package and a second package on the first package. The first package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die and an IC device are mounted on the bottom substrate in a side-by-side configuration. The logic die has a thickness not less than 125 micrometer. Copper cored solder balls are disposed between around the logic die and the IC device to electrically connect the bottom substrate with the top substrate. A sealing resin is filled into the gap between the bottom substrate and the top substrate and seals the logic die, the IC device, and the copper cored solder balls in the gap.Type: ApplicationFiled: May 30, 2023Publication date: September 28, 2023Applicant: MEDIATEK INC.Inventors: Ta-Jen Yu, Wen-Chin Tsai, Isabella Song, Tai-Yu Chen, Che-Hung Kuo, Hsing-Chih Liu, Shih-Chin Lin, Wen-Sung Hsu
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Publication number: 20230282626Abstract: A high-bandwidth package-on-package (HBPoP) structure includes a first package structure and a second package structure disposed over the first package structure. The first package structure includes a first package substrate, a semiconductor die, an interposer, and a molding material. The first package substrate is formed of a silicon and/or ceramic material. The semiconductor die is disposed over the first package substrate. The interposer is disposed over the semiconductor die and is formed of a silicon and/or ceramic material. The molding material is disposed between the first package substrate and the interposer and surrounds the semiconductor die.Type: ApplicationFiled: February 2, 2023Publication date: September 7, 2023Inventors: Tai-Yu CHEN, Bo-Jiun YANG, Tsung-Yu PAN, Yin-Fa CHEN, Ta-Jen YU, Bo-Hao MA, Wen-Sung HSU, Yao-Pang HSU
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Publication number: 20230282604Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die is mounted on a top surface of the bottom substrate in a flip-chip fashion. The logic die has a thickness of 125-350 micrometers. The logic die comprises an active front side, a passive rear side, and an input/output pad provided on the active front side. A plurality of copper cored solder balls is disposed between the bottom substrate and the top substrate around the logic die to electrically connect the bottom substrate with the top substrate. A sealing resin fills in the gap between the bottom substrate and the top substrate and seals the logic die and the plurality of copper cored solder balls in the gap.Type: ApplicationFiled: February 7, 2023Publication date: September 7, 2023Applicant: MEDIATEK INC.Inventors: Ta-Jen Yu, Tai-Yu Chen, Shih-Chin Lin, Isabella Song, Wen-Chin Tsai
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Publication number: 20230282625Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die is mounted on a top surface of the bottom substrate. The logic die has a thickness of 125-350 micrometers. A plurality of copper cored solder balls is disposed between the bottom substrate and the top substrate around the logic die to electrically connect the bottom substrate with the top substrate. A sealing resin fills into the gap between the bottom substrate and the top substrate and sealing the logic die and the plurality of copper cored solder balls in the gap.Type: ApplicationFiled: February 9, 2023Publication date: September 7, 2023Applicant: MEDIATEK INC.Inventors: Ta-Jen Yu, Shih-Chin Lin, Tai-Yu Chen, Bo-Jiun Yang, Bing-Yeh Lin, Yung-Cheng Huang, Wen-Sung Hsu, Bo-Hao Ma, Isabella Song
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Publication number: 20230260866Abstract: A semiconductor package structure includes a package substrate, a semiconductor die, an interposer, an adhesive layer, and a molding material. The semiconductor die is disposed over the package substrate. The interposer is disposed over the semiconductor die. The adhesive layer connects the semiconductor die and the interposer. The molding material surrounds the semiconductor die and the adhesive layer.Type: ApplicationFiled: January 20, 2023Publication date: August 17, 2023Inventors: Yin-Fa CHEN, Bo-Jiun YANG, Ta-Jen YU, Bo-Hao MA, Chih-Wei CHANG, Tsung-Yu PAN, Tai-Yu CHEN, Shih-Chin LIN, Wen-Sung HSU
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Publication number: 20230073399Abstract: A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.Type: ApplicationFiled: November 17, 2022Publication date: March 9, 2023Applicant: MediaTek Inc.Inventors: Yen-Yao Chi, Nai-Wei Liu, Ta-Jen Yu, Tzu-Hung Lin, Wen-Sung Hsu, Shih-Chin Lin
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Publication number: 20230046413Abstract: A semiconductor assembly package is provided. The semiconductor package assembly includes a system-on-chip (SOC) package, a memory package and a heat spreader. The SOC package includes a logic die and a first substrate. The logic die has pads on it. The first substrate is electrically connected to the logic die by the pads. The memory package includes a second substrate and a memory die. The second substrate has a top surface and a bottom surface. The memory die is mounted on the top surface of the second substrate and is electrically connected to the second substrate using bonding wires. The heat spreader is disposed between the SOC package and the memory package, wherein the heat spreader is in contact with a back surface of the logic die away from the pads.Type: ApplicationFiled: July 15, 2022Publication date: February 16, 2023Inventors: Tai-Yu CHEN, Chin-Lai CHEN, Hsiao-Yun CHEN, Wen-Sung HSU, Haw-Kuen SU, Duen-Yi HO, Bo-Jiun YANG, Ta-Jen YU, Bo-Hao MA
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Publication number: 20220392839Abstract: A semiconductor package structure including a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. A first protective insulating layer covers the first and third surfaces of the semiconductor die. A redistribution layer (RDL) structure is electrically coupled to the semiconductor die and surrounded by the first protective insulating layer on the first surface of the semiconductor die. A first passivation layer covers the first protective insulating layer and the RDL structure. At least one conductive structure passes through the first passivation layer and is electrically coupled to the RDL structure. A method of forming the semiconductor package is also provided.Type: ApplicationFiled: August 12, 2022Publication date: December 8, 2022Applicant: MediaTek Inc.Inventors: Yen-Yao Chi, Nai-Wei Liu, Ta-Jen Yu, Tzu-Hung Lin, Wen-Sung Hsu
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Patent number: 11469201Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.Type: GrantFiled: December 19, 2019Date of Patent: October 11, 2022Assignee: MediaTek Inc.Inventors: Tzu-Hung Lin, Wen-Sung Hsu, Ta-Jen Yu, Andrew C. Chang
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Patent number: 11450606Abstract: A semiconductor package structure including a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. A first protective insulating layer covers the first and third surfaces of the semiconductor die. A redistribution layer (RDL) structure is electrically coupled to the semiconductor die and surrounded by the first protective insulating layer on the first surface of the semiconductor die. A first passivation layer covers the first protective insulating layer and the RDL structure. At least one conductive structure passes through the first passivation layer and is electrically coupled to the RDL structure. A method of forming the semiconductor package is also provided.Type: GrantFiled: June 3, 2019Date of Patent: September 20, 2022Assignee: MediaTek Inc.Inventors: Yen-Yao Chi, Nai-Wei Liu, Tzu-Hung Lin, Ta-Jen Yu, Wen-Sung Hsu
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Patent number: 10916449Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a base. The base has a device-attach surface. A radio-frequency (RF) device is embedded in the base. The RF device is close to the device-attach surface.Type: GrantFiled: January 15, 2020Date of Patent: February 9, 2021Assignee: MediaTek Inc.Inventors: Wen-Sung Hsu, Ta-Jen Yu
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Publication number: 20200312732Abstract: A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.Type: ApplicationFiled: June 17, 2020Publication date: October 1, 2020Inventors: Yen-Yao CHI, Nai-Wei LIU, Ta-Jen YU, Tzu-Hung LIN, Wen-Sung HSU, Shih-Chin LIN
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Patent number: 10756040Abstract: The invention provides a semiconductor package. The semiconductor package includes a semiconductor die and a conductive pillar bump structure and a conductive plug. The semiconductor die has a die pad thereon. The conductive pillar bump structure is positioned overlying the die pad. The conductive pillar bump structure includes an under bump metallurgy (UBM) stack having a first diameter and a conductive plug on the UBM stack. The conductive plug has a second diameter that is different than the first diameter.Type: GrantFiled: January 26, 2018Date of Patent: August 25, 2020Assignee: MediaTek Inc.Inventors: Ta-Jen Yu, Chi-Yuan Chen, Wen-Sung Hsu
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Publication number: 20200176408Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.Type: ApplicationFiled: December 19, 2019Publication date: June 4, 2020Applicant: MediaTek Inc.Inventors: Tzu-Hung Lin, Wen-Sung Hsu, Ta-Jen Yu, Andrew C. Chang
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Publication number: 20200152479Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a base. The base has a device-attach surface. A radio-frequency (RF) device is embedded in the base. The RF device is close to the device-attach surface.Type: ApplicationFiled: January 15, 2020Publication date: May 14, 2020Applicant: MediaTek Inc.Inventors: Wen-Sung Hsu, Ta-Jen Yu