Abstract: A current steering converter fabricated using a predetermined integrated circuit technology includes a unary portion having one or more current sources and a binary portion including a plurality of switches controlled by a decoder, the switches coupled to a converter output; and a plurality of devices commonly connected at a first end and coupled to each respective switch at a second end, wherein each device size comprises (W/L)*M, where W/L is a width and length of the device and M is an integer representing multiple number.

Abstract: A method of increasing SAR ADC conversion rate and reducing power consumption by employing a new timing scheme and minimizing timing delay for each bit-test during binary-search process. The high frequency clock input requirement is eliminated and higher speed rate can be achieved in SAR ADC.

Abstract: A high resolution timing device is provided. The high resolution timing device includes a first and a second clock delay circuits. The first clock delay circuit receives an input reference clock signal to generate a first multiple frequency output clock signal, divide the first multiple frequency output clock signal to generate a first original frequency output clock signal and perform a clock-delaying process thereon according to the first multiple frequency output clock signal to generate first clock-delayed signals. The second clock delay circuit receives one of the first clock-delayed signals to generate a second multiple frequency output clock signal, divide the second multiple frequency output clock signal to generate a second original frequency output clock signal and perform the clock-delaying process thereon according to the second multiple frequency output clock signal to generate second clock-delayed signals.

Abstract: A data converter includes a single-end capacitive digital to analog converter (DAC); a transconductance (GM) buffer having an output, a positive input coupled to the DAC and a negative input coupled to the output; a resistor and a capacitor load in parallel coupled to the output at one terminal and to ground at the other terminal. The developed architecture of comprising single end capacitive DAC and GM-based buffer provides fast conversion rate, low current consumption, small silicon area and wide supply range for general-purpose auxiliary DAC applications.

Abstract: A high resolution timing device is provided. The high resolution timing device includes a first and a second dock delay circuits. The first clock delay circuit receives an input reference clock signal to generate a first multiple frequency output clock signal, divide the first multiple frequency output clock signal to generate a first original frequency output clock signal and perform a clock-delaying process thereon according to the first multiple frequency output clock signal to generate first clock-delayed signals. The second clock delay circuit receives one of the first clock-delayed signals to generate a second multiple frequency output clock signal, divide the second multiple frequency output clock signal to generate a second original frequency output clock signal and perform the clock-delaying process thereon according to the second multiple frequency output clack signal to generate second clock-delayed signals.

Abstract: A path sharing transceiver array architecture is disclosed. A plurality of channels are linked to antennas of an array for transmitting and receiving wireless signals that are offset in one of phase or time relative to one another. Each channel is associated with a delay element. In the receiving case, an offset signal is received at a first channel, processed, and shifted by a first delay element. The resulting signal is combined with the processed signal of a second, adjacent channel where a phase or time delayed signal is received. The combined signal is then shifted by a second delay element to produce a net signal. The first delay element is used to generate a shifted signal for both the first and second channel. The architecture can be extended to another number of channels.

Abstract: A tunable laser system is provided. The tunable laser system includes a light source, a grating, a corner mirror array, and a receiver. In which, the light source emits a beam, and the grating is located in front of the light source for reflecting the beam to form a first reflective beam. Also, the corner mirror array is located in front of the grating for receiving the first reflective beam and forms a second reflective beam accordingly. In addition, the receiver is used to receive a third reflective beam formed from reflecting the second reflective beam through the grating.

Abstract: A path sharing transceiver array architecture is disclosed. A plurality of channels are linked to antennas of an array for transmitting and receiving wireless signals that are offset in one of phase or time relative to one another. Each channel is associated with a delay element. In the receiving case, an offset signal is received at a first channel, processed, and shifted by a first delay element. The resulting signal is combined with the processed signal of a second, adjacent channel where a phase or time delayed signal is received. The combined signal is then shifted by a second delay element to produce a net signal. The first delay element is used to generate a shifted signal for both the first and second channel. The architecture can be extended to another number of channels.

Abstract: A tunable laser system is provided. The tunable laser system includes a light source, a grating, a corner mirror array, and a receiver. In which, the light source emits a beam, and the grating is located in front of the light source for reflecting the beam to form a first reflective beam. Also, the corner mirror array is located in front of the grating for receiving the first reflective beam and forms a second reflective beam accordingly. In addition, the receiver is used to receive a third reflective beam formed from reflecting the second reflective beam through the grating.