Patents by Inventor Ta-Wen Liao

Ta-Wen Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250087650
    Abstract: A display panel includes a driving backplane, a light emitting component, a reflective structure and a bridging component. The driving backplane has a first pad and a second pad separated from each other. The light emitting component has a first electrode and a second electrode. The first electrode is electrically connected to the first pad of the driving backplane, and the first electrode is located between the second electrode and the first pad of the driving backplane. The reflective structure is disposed on the driving backplane and located at a periphery of the light emitting component. The bridging component is disposed on the light emitting component. One end of the bridging component is electrically connected to the second electrode. The bridging component passes across at least one portion of the reflective structure. The other end of the bridging component is electrically connected to the second pad of the driving backplane.
    Type: Application
    Filed: December 27, 2023
    Publication date: March 13, 2025
    Inventors: Yang-En WU, Chieh-Ming Chen, Bo-Ru Jian, Kuo-Hsuan Huang, Ta-Wen Liao, Yu-Chin Wu
  • Publication number: 20250008649
    Abstract: A circuit board includes a plurality of pixel areas. Each pixel area includes a plurality of electrode pad groups. The electrode pad groups are arranged in a first direction. Each of the electrode pad groups includes a first electrode pad, a second electrode pad, and a third electrode pad. The first electrode pad, the second electrode pad, and the third electrode pad are arranged in a second direction. The second direction is different from the first direction. The first electrode pad is disposed between the second electrode pad and the third electrode pad. The first electrode pad is configured to provide a first voltage potential. The second electrode pad and the third electrode pad are configured to provide a second voltage potential. The first voltage potential is different from the second voltage potential.
    Type: Application
    Filed: December 18, 2023
    Publication date: January 2, 2025
    Inventors: Chieh-Ming CHEN, Kuo-Hsuan Huang, Bo-Ru Jian, Jui-Ping Yu, Ta-Wen Liao, Yu-Chin Wu
  • Publication number: 20240250092
    Abstract: A micro light-emitting diode display device includes a circuit substrate, a first light-emitting element, a second light-emitting element, a third light-emitting element, and a conductive layer. The first light-emitting element, the second light-emitting element, and the third light-emitting element are disposed on the circuit substrate and have a first electrode and a second electrode, respectively. The first electrode of the first light-emitting element, the first electrode of the second light-emitting element, and the first electrode of the third light-emitting element are electrically connected to the circuit substrate. The second electrode of the first light-emitting element and the second electrode of the second light-emitting element are a continuous semiconductor material layer. The second electrode of the third light-emitting element is separated from the second electrode of the first light-emitting element and the second electrode of the second light-emitting element.
    Type: Application
    Filed: November 28, 2023
    Publication date: July 25, 2024
    Inventors: Chao-Kun HUANG, Kuo-Hsuan Huang, Chieh-Ming Chen, Bo-Ru Jian, Ta-Wen Liao
  • Publication number: 20240234652
    Abstract: A micro light-emitting diode display device includes a substrate, a first planarization layer, a first light-emitting element, and a second planarization layer. The first planarization layer is disposed on the substrate and has a first opening. The first opening has a first opening inner wall. The first light-emitting element is disposed on the substrate, in the first opening, and separated from the first opening inner wall. The second planarization layer is disposed on the substrate and between the first planarization layer and the first light-emitting element. The second planarization layer is in contact with the first light-emitting element.
    Type: Application
    Filed: October 19, 2023
    Publication date: July 11, 2024
    Inventors: Bin-Cheng LIN, Chieh-Ming Chen, Bo-Ru Jian, Chi-Sheng Liao, Ta-Wen Liao
  • Publication number: 20240162406
    Abstract: A display panel including an array substrate, a light-emitting diode chip, a photosensitive material layer and a photosensitive material layer. The array substrate includes a first electrode pad and a second electrode pad adjacent to the first electrode pad. The light-emitting diode chip includes a first electrode and a second electrode at opposite sides of the light-emitting diode chip, and the first electrode is connected with the first electrode pad. The photosensitive material layer is over the array substrate and surrounds the light-emitting diode chip, in which the photosensitive material layer includes an opening exposing the second electrode pad, a sidewall of the opening has a first portion and a second portion, a slope of the first portion is greater than a slope of the second portion. The transparent conductive layer is over the photosensitive material layer and electrically connects the second electrode pad and the second electrode.
    Type: Application
    Filed: October 4, 2023
    Publication date: May 16, 2024
    Inventors: Chieh-Ming CHEN, Chou-Huan Yu, Bo-ru Jian, Ta-Wen Liao
  • Publication number: 20240136481
    Abstract: A micro light-emitting diode display device includes a substrate, a first planarization layer, a first light-emitting element, and a second planarization layer. The first planarization layer is disposed on the substrate and has a first opening. The first opening has a first opening inner wall. The first light-emitting element is disposed on the substrate, in the first opening, and separated from the first opening inner wall. The second planarization layer is disposed on the substrate and between the first planarization layer and the first light-emitting element. The second planarization layer is in contact with the first light-emitting element.
    Type: Application
    Filed: October 18, 2023
    Publication date: April 25, 2024
    Inventors: Bin-Cheng LIN, Chieh-Ming Chen, Bo-Ru Jian, Chi-Sheng Liao, Ta-Wen Liao
  • Publication number: 20230276580
    Abstract: A circuit board structure for a display device includes a substrate, a bump, a protective layer, and a moisture-resistant layer. The substrate includes a first surface and a second surface opposite to the first surface. The bump is disposed on the first surface of the substrate and includes a first inorganic material. The protective layer is disposed on the first surface of the substrate. The protective layer includes an organic material and a first opening, in which the bump is positioned in the first opening. The moisture-resistant layer entirely covers the protective layer. The moisture-resistant layer includes a second inorganic material and a second opening, in which a portion of the bump is exposed in the second opening.
    Type: Application
    Filed: February 15, 2023
    Publication date: August 31, 2023
    Inventors: Chi-Sheng LIAO, Bo-Ru JIAN, Bin-Cheng LIN, Ta-Wen LIAO
  • Publication number: 20230275117
    Abstract: A display panel includes a substrate, an LED array disposed on the front side of the substrate, a driving circuit disposed on the front side of the substrate and connected to the LED array, a connecting line and a transparent conductive layer disposed on the back side of the substrate. The connecting line is spaced apart with a side surface of the substrate thereby defining a cutting area. The transparent conductive layer extends from the cutting area and at least partially covering the connecting line. The display panel further includes a first passivation layer and a conductive layer. The first passivation layer is disposed on the transparent conductive layer and the connecting line. The side surfaces of the first passivation layer, the transparent conductive layer, and the substrate are aligned. The conductive layer penetrates the first passivation layer to connect the transparent conductive layer to the driving circuit.
    Type: Application
    Filed: January 30, 2023
    Publication date: August 31, 2023
    Inventors: Bin-Cheng LIN, Bo-Ru Jian, Chi-Sheng Liao, Ta-Wen Liao
  • Patent number: 9341950
    Abstract: An exposure apparatus is provided and adapted for exposing a photoresist layer on a layer to form a plurality of strip exposed patterns. The exposure apparatus includes a light source, a lens group and a mask. The lens group is disposed between the photoresist layer and the light source and includes a plurality of strip lens parallel to each other, wherein an overlapping region between any two neighboring strip lens is defined as a lens connecting region, and the other regions excluding the lens connecting regions are defined as lens regions. The mask is disposed between the photoresist layer and the lens group and includes a plurality of shielding patterns, wherein an outline of the shielding patterns corresponds to the strip exposed patterns, each shielding pattern has a strip opening, and an extension direction of the strip openings is substantially parallel to an extension direction of the shielding patterns.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: May 17, 2016
    Assignee: Au Optronics Corporation
    Inventors: Hsiang-Chih Hsiao, Ta-Wen Liao, Tzu-Min Yang, Shan-Fang Chen, Ya-Ping Chang, Chi-Hung Yang, Chung-Yuan Liao
  • Publication number: 20150253672
    Abstract: An exposure apparatus is provided and adapted for exposing a photoresist layer on a layer to form a plurality of strip exposed patterns. The exposure apparatus includes a light source, a lens group and a mask. The lens group is disposed between the photoresist layer and the light source and includes a plurality of strip lens parallel to each other, wherein an overlapping region between any two neighboring strip lens is defined as a lens connecting region, and the other regions excluding the lens connecting regions are defined as lens regions. The mask is disposed between the photoresist layer and the lens group and includes a plurality of shielding patterns, wherein an outline of the shielding patterns corresponds to the strip exposed patterns, each shielding pattern has a strip opening, and an extension direction of the strip openings is substantially parallel to an extension direction of the shielding patterns.
    Type: Application
    Filed: May 27, 2015
    Publication date: September 10, 2015
    Inventors: Hsiang-Chih Hsiao, Ta-Wen Liao, Tzu-Min Yang, Shan-Fang Chen, Ya-Ping Chang, Chi-Hung Yang, Chung-Yuan Liao
  • Patent number: 9122162
    Abstract: An exposure apparatus is provided and adapted for exposing a photoresist layer on a layer to form a plurality of strip exposed patterns. The exposure apparatus includes a light source, a lens group and a mask. The lens group is disposed between the photoresist layer and the light source and includes a plurality of strip lens parallel to each other, wherein an overlapping region between any two neighboring strip lens is defined as a lens connecting region, and the other regions excluding the lens connecting regions are defined as lens regions. The mask is disposed between the photoresist layer and the lens group and includes a plurality of shielding patterns, wherein an outline of the shielding patterns corresponds to the strip exposed patterns, each shielding pattern has a strip opening, and an extension direction of the strip openings is substantially parallel to an extension direction of the shielding patterns.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 1, 2015
    Assignee: Au Optronics Corporation
    Inventors: Hsiang-Chih Hsiao, Ta-Wen Liao, Tzu-Min Yang, Shan-Fang Chen, Ya-Ping Chang, Chi-Hung Yang, Chung-Yuan Liao
  • Patent number: 8811567
    Abstract: A shift register for providing a plurality of gate signals includes an Nth stage shift register unit and an (N+1)th stage shift register unit. The Nth stage shift register unit includes a first pull up unit, a first driving unit, a first control unit and a first auxiliary pull down unit. The (N+1)th stage shift register unit includes a second pull up unit, a second driving unit, a first pull down unit and a second auxiliary pull down unit. The first and second pull up units are both coupled to the first and second driving units for controlling the first and second driving units to generate gate signals. The first and second auxiliary pull down units are both coupled to the first control unit for pulling down the gate signals.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: August 19, 2014
    Assignee: AU Optronics Corp.
    Inventors: Chen-Yi Wu, Ta-Wen Liao
  • Publication number: 20140010341
    Abstract: A shift register for providing a plurality of gate signals includes an Nth stage shift register unit and an (N+1)th stage shift register unit. The Nth stage shift register unit includes a first pull up unit, a first driving unit, a first control unit and a first auxiliary pull down unit. The (N+1)th stage shift register unit includes a second pull up unit, a second driving unit, a first pull down unit and a second auxiliary pull down unit. The first and second pull up units are both coupled to the first and second driving units for controlling the first and second driving units to generate gate signals. The first and second auxiliary pull down units are both coupled to the first control unit for pulling down the gate signals.
    Type: Application
    Filed: February 19, 2013
    Publication date: January 9, 2014
    Applicant: AU OPTRONICS CORP.
    Inventors: Chen-Yi Wu, Ta-Wen Liao
  • Publication number: 20130235316
    Abstract: An exposure apparatus is provided and adapted for exposing a photoresist layer on a layer to form a plurality of strip exposed patterns. The exposure apparatus includes a light source, a lens group and a mask. The lens group is disposed between the photoresist layer and the light source and includes a plurality of strip lens parallel to each other, wherein an overlapping region between any two neighboring strip lens is defined as a lens connecting region, and the other regions excluding the lens connecting regions are defined as lens regions. The mask is disposed between the photoresist layer and the lens group and includes a plurality of shielding patterns, wherein an outline of the shielding patterns corresponds to the strip exposed patterns, each shielding pattern has a strip opening, and an extension direction of the strip openings is substantially parallel to an extension direction of the shielding patterns.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 12, 2013
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Hsiang-Chih Hsiao, Ta-Wen Liao, Tzu-Min Yang, Shan-Fang Chen, Ya-Ping Chang, Chi-Hung Yang, Chung-Yuan Liao
  • Patent number: 8530144
    Abstract: A method is provided for fabricating source/drain electrodes of a thin film transistor. The method generally provides a substrate having a first gate electrode and a second gate electrode adjacent and electrically connected. The method further provides coating a photoresist layer on the metal layer, and performing an exposure process on the photoresist layer by a photomask. The method further performs a development process on the exposed photoresist layer to form a photoresist pattern layer with different thicknesses on the metal layer, and then etches the metal layer using the photoresist pattern layer as an etch mask, to form a pair of first source/drain electrodes on the first gate electrode and a pair of second source/drain electrodes on the second gate electrode.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: September 10, 2013
    Assignee: AU Optronics Corp.
    Inventors: Zong-Long Jhang, Chia-Ming Chang, Hsiang-Chih Hsiao, Chun-Yi Chiang, Che-Yung Lai, Chou-Huan Yu, Ta-Wen Liao
  • Patent number: 8427631
    Abstract: An exposure apparatus is provided and adapted for exposing a photoresist layer on a layer to form a plurality of strip exposed patterns. The exposure apparatus includes a light source, a lens group and a mask. The lens group is disposed between the photoresist layer and the light source and includes a plurality of strip lens parallel to each other, wherein an overlapping region between any two neighboring strip lens is defined as a lens connecting region, and the other regions excluding the lens connecting regions are defined as lens regions. The mask is disposed between the photoresist layer and the lens group and includes a plurality of shielding patterns, wherein an outline of the shielding patterns corresponds to the strip exposed patterns, each shielding pattern has a strip opening, and an extension direction of the strip openings is substantially parallel to an extension direction of the shielding patterns.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: April 23, 2013
    Assignee: Au Optronics Corporation
    Inventors: Hsiang-Chih Hsiao, Ta-Wen Liao, Chi-Min Yang, Shan-Fang Chen, Ya-Ping Chang, Chi-Hung Yang, Chung-Yuan Liao
  • Publication number: 20120270397
    Abstract: A method is provided for fabricating source/drain electrodes of a thin film transistor. The method generally provides a substrate having a first gate electrode and a second gate electrode adjacent and electrically connected. The method further provides coating a photoresist layer on the metal layer, and performing an exposure process on the photoresist layer by a photomask. The method further performs a development process on the exposed photoresist layer to form a photoresist pattern layer with different thicknesses on the metal layer, and then etches the metal layer using the photoresist pattern layer as an etch mask, to form a pair of first source/drain electrodes on the first gate electrode and a pair of second source/drain electrodes on the second gate electrode.
    Type: Application
    Filed: March 8, 2012
    Publication date: October 25, 2012
    Applicant: AU OPTRONICS CORP.
    Inventors: Zong-Long Jhang, Chia-Ming Chang, Hsiang-Chih Hsiao, Chun-Yi Chiang, Che-Yung Lai, Chou-Huan Yu, Ta-Wen Liao
  • Patent number: 8278157
    Abstract: Methods for fabricating array substrates are provided. A method for fabricating an array substrate includes forming a first metal layer over a substrate and then patterned by a first photolithography to forming a gate line, a gate electrode connecting the gate line, and a pad over the substrate. An insulating layer, a semiconductor layer, and an ohmic contact layer are formed over the substrate to cover the gate line, the gate electrode and the pad. The ohmic contact layer, the semiconductor layer, and portions of the insulating layer are patterned by a second photolithography to forming a semiconductor structure over the substrate and a via hole in the insulating layer over the pad to exposing a part of the pad.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: October 2, 2012
    Assignee: AU Optronics Corp.
    Inventor: Ta-Wen Liao
  • Patent number: 8153337
    Abstract: A photomask for fabricating a thin film transistor (TFT) is disclosed. The photomask includes a translucent layer disposed on a transparent substrate and covering U-shaped and rectangular channel-forming regions of the transparent substrate. First and second light-shielding layers are disposed on the translucent layer and located at the outer and inner sides of the U-shaped channel-forming region, respectively, and third and fourth light-shielding layers are disposed on the translucent layer and located at opposite sides of the rectangular channel-forming region, respectively, to serve as source/drain-forming regions. An end of the third light-shielding layer extends to the first light-shielding layer. A plurality of first light-shielding islands is disposed on the translucent layer and located within the rectangular channel-forming region. A method for fabricating source/drain electrodes of a TFT is also disclosed.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: April 10, 2012
    Assignee: AU Optronics Corp.
    Inventors: Zong-Long Jhang, Chia-Ming Chang, Hsiang-Chih Hsiao, Chun-Yi Chiang, Che-Yung Lai, Chou-Huan Yu, Ta-Wen Liao
  • Publication number: 20110223393
    Abstract: An exposure apparatus is provided and adapted for exposing a photoresist layer on a layer to form a plurality of strip exposed patterns. The exposure apparatus includes a light source, a lens group and a mask. The lens group is disposed between the photoresist layer and the light source and includes a plurality of strip lens parallel to each other, wherein an overlapping region between any two neighboring strip lens is defined as a lens connecting region, and the other regions excluding the lens connecting regions are defined as lens regions. The mask is disposed between the photoresist layer and the lens group and includes a plurality of shielding patterns, wherein an outline of the shielding patterns corresponds to the strip exposed patterns, each shielding pattern has a strip opening, and an extension direction of the strip openings is substantially parallel to an extension direction of the shielding patterns.
    Type: Application
    Filed: November 17, 2010
    Publication date: September 15, 2011
    Applicant: Au Optronics Corporation
    Inventors: Hsiang-Chih Hsiao, Ta-Wen Liao, Chi-Min Yang, Shan-Fang Chen, Ya-Ping Chang, Chi-Hung Yang, Chung-Yuan Liao