Patents by Inventor Ta-Wen Liao

Ta-Wen Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7989243
    Abstract: A pixel structure fabricating method is provided. A gate is formed on a substrate. A gate insulation layer covering the gate is formed on the substrate. A channel layer, a source, and a drain are simultaneously formed on the gate insulation layer above the gate. The gate, channel layer, source, and drain form a thin film transistor (TFT). A passivation layer is formed on the TFT and the gate insulation layer. A black matrix is formed on the passivation layer. The black matrix has a contact opening above the drain and a color filter containing opening. A color filer layer is formed within the color filter containing opening through inkjet printing. A dielectric layer is formed on the black matrix and the color filter layer. The dielectric layer and the passivation layer are patterned to expose the drain. A pixel electrode electrically connected to the drain is formed.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: August 2, 2011
    Assignee: Au Optronics Corporation
    Inventors: Ta-Wen Liao, Chen-Pang Tung, Chia-Ming Chang, Zong-Long Jhang, Che-Yung Lai, Chun-Yi Chiang, Chou-Huan Yu, Hsiang-Chih Hsiao, Han-Tang Chou, Jun-Kai Chang
  • Publication number: 20110053323
    Abstract: A photomask for fabricating a thin film transistor (TFT) is disclosed. The photomask includes a translucent layer disposed on a transparent substrate and covering U-shaped and rectangular channel-forming regions of the transparent substrate. First and second light-shielding layers are disposed on the translucent layer and located at the outer and inner sides of the U-shaped channel-forming region, respectively, and third and fourth light-shielding layers are disposed on the translucent layer and located at opposite sides of the rectangular channel-forming region, respectively, to serve as source/drain-forming regions. An end of the third light-shielding layer extends to the first light-shielding layer. A plurality of first light-shielding islands is disposed on the translucent layer and located within the rectangular channel-forming region. A method for fabricating source/drain electrodes of a TFT is also disclosed.
    Type: Application
    Filed: December 3, 2009
    Publication date: March 3, 2011
    Applicant: AU OPTRONICS CORP.
    Inventors: Zong-Long Jhang, Chia-Ming Chang, Hsiang-Chih Hsiao, Chun-Yi Chiang, Che-Yung Lai, Chou-Huan Yu, Ta-Wen Liao
  • Patent number: 7897442
    Abstract: A method for fabricating a pixel structure is disclosed. A substrate is provided. A first conductive layer is formed on the substrate, and a first shadow mask exposing a portion of the first conductive layer is disposed over the first conductive layer. Laser is used to irradiate the first conductive layer for removing the part of the first conductive layer and forming a gate. A gate dielectric layer is formed on the substrate to cover the gate. A channel layer is formed on the gate dielectric layer over the gate. A source and a drain are formed on the channel layer and respectively above both sides of the gate. A patterned passivation layer is formed to cover the channel layer and expose the drain. An electrode material layer is formed to cover the patterned passivation layer and the exposed drain.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: March 1, 2011
    Assignee: Au Optronics Corporation
    Inventors: Ta-Wen Liao, Chih-Chun Yang, Ming-Yuan Huang, Han-Tu Lin, Chih-Hung Shih, Chin-Yueh Liao, Chia-Chi Tsai
  • Patent number: 7816159
    Abstract: A method for fabricating a pixel structure includes following steps. First, a substrate is provided. Next, a first conductive layer is formed on the substrate. Next, a first shadow mask is disposed over the first conductive layer. Next, a laser is applied through the first shadow mask to irradiate the first conductive layer to form a gate. Next, a gate dielectric layer is formed on the substrate to cover the gate. After that, a channel layer, a source and a drain are simultaneously formed on the gate dielectric layer over the gate, wherein the gate, the channel layer, the source and the drain together form a thin film transistor. A patterned passivation layer is formed on the thin film transistor and the patterned passivation layer exposes a part of the drain. Furthermore, a pixel electrode electrically connecting to the drain is formed.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: October 19, 2010
    Assignee: Au Optronics Corporation
    Inventors: Kuo-Lung Fang, Chih-Chun Yang, Ming-Yuan Huang, Han-Tu Lin, Chih-Hung Shih, Ta-Wen Liao, Shiun-Chang Jan, Chia-Chi Tsai
  • Patent number: 7811867
    Abstract: A method for manufacturing a pixel structure is provided. A gate and a gate insulating layer are sequentially formed on a substrate. A semiconductor layer and a second metal layer are sequentially formed on the gate insulating layer. The semiconductor layer and the second metal layer are patterned to form a channel layer, a source and a drain by using a patterned photoresist layer formed thereon, wherein the source and drain are disposed on a portion of the channel layer. The gate, channel, source and drain form a thin film transistor. A passivation layer is formed on the patterned photoresist layer, the gate insulating layer and the thin film transistor. Then, the patterned photoresist layer is removed, such that the passivation layer thereon is removed simultaneously to form a patterned passivation layer and the drain is exposed. A pixel electrode is formed on the patterned passivation layer and the drain.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: October 12, 2010
    Assignee: Au Optronics Corporation
    Inventors: Chih-Chun Yang, Ming-Yuan Huang, Han-Tu Lin, Chih-Hung Shih, Ta-Wen Liao, Kuo-Lung Fang
  • Patent number: 7682884
    Abstract: A method for fabricating a pixel structure using a laser ablation process is provided. This fabrication method forms a gate, a channel layer, a source, a drain, a passivation layer, and a pixel electrode sequentially by using a laser ablation process. Particularly, the fabrication method is not similar to a photolithography and etching process, so as to reduce the complicated photolithography and etching processes, such as spin coating process, soft-bake, hard-bake, exposure, developing, etching, and stripping. Therefore, the fabrication method simplifies the process and thus reduces the fabrication cost.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: March 23, 2010
    Assignee: Au Optronics Corporation
    Inventors: Han-Tu Lin, Chih-Chun Yang, Ming-Yuan Huang, Chih-Hung Shih, Ta-Wen Liao, Chia-Chi Tsai
  • Publication number: 20100055853
    Abstract: A method for manufacturing a pixel structure is provided. A gate and a gate insulating layer are sequentially formed on a substrate. A semiconductor layer and a second metal layer are sequentially formed on the gate insulating layer. The semiconductor layer and the second metal layer are patterned to form a channel layer, a source and a drain by using a patterned photoresist layer formed thereon, wherein the source and drain are disposed on a portion of the channel layer. The gate, channel, source and drain form a thin film transistor. A passivation layer is formed on the patterned photoresist layer, the gate insulating layer and the thin film transistor. Then, the patterned photoresist layer is removed, such that the passivation layer thereon is removed simultaneously to form a patterned passivation layer and the drain is exposed. A pixel electrode is formed on the patterned passivation layer and the drain.
    Type: Application
    Filed: November 12, 2009
    Publication date: March 4, 2010
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Chih-Chun Yang, Ming-Yuan Huang, Han-Tu Lin, Chih-Hung Shih, Ta-Wen Liao, Kuo-Lung Fang, Chia-Chi Tsai
  • Patent number: 7648865
    Abstract: A method for manufacturing a pixel structure is provided. First, a gate and a gate insulating layer are sequentially formed on the substrate. A channel layer and a second metal layer are sequentially formed on the gate insulating layer. The second metal layer is patterned to form a source and a drain by using a patterned photoresist layer formed thereon, wherein the source and the drain are disposed on a portion of the channel layer. The gate, the channel, the source and the drain form a thin film transistor. A passivation layer is formed on the patterned photoresist layer, the gate insulating layer and the thin film transistor. Then, the patterned photoresist layer is removed, such that the passivation layer thereon is removed simultaneously to form a patterned passivation layer and the drain is exposed. A pixel electrode is formed on the patterned passivation layer and the drain.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: January 19, 2010
    Assignee: Au Optronics Corporation
    Inventors: Chih-Chun Yang, Ming-Yuan Huang, Han-Tu Lin, Chih-Hung Shih, Ta-Wen Liao, Kuo-Lung Fang, Chia-Chi Tsai
  • Patent number: 7645649
    Abstract: A pixel structure fabricating method is provided. A gate and a gate insulation layer covering the gate are formed on a substrate. A channel layer is formed on the gate insulation layer. A conductive layer is formed on the channel layer and gate insulation layer. A black matrix having a color filer layer accommodating opening is formed on the conductive layer. The black matrix includes a first block and a second block which is thicker than the first block. The conductive layer is patterned with the black matrix as a mask to form a source and a drain on the channel layer. A color filter layer is formed within the color filter layer accommodating opening through inkjet printing. A dielectric layer is formed on the black matrix and color filter layer. The dielectric layer is patterned to expose the drain. A pixel electrode electrically connected to the drain is formed.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: January 12, 2010
    Assignee: Au Optronics Corporation
    Inventors: Che-Yung Lai, Zong-Long Jhang, Chia-Chi Tsai, Chen-Pang Tung, Chia-Ming Chang, Chun-Yi Chiang, Chou-Huan Yu, Hsiang-Chih Hsiao, Han-Tang Chou, Jun-Kai Chang, Ta-Wen Liao
  • Publication number: 20100003774
    Abstract: A pixel structure fabricating method is provided. A gate is formed on a substrate. A gate insulation layer covering the gate is formed on the substrate. A channel layer, a source, and a drain are simultaneously formed on the gate insulation layer above the gate. The gate, channel layer, source, and drain form a thin film transistor (TFT). A passivation layer is formed on the TFT and the gate insulation layer. A black matrix is formed on the passivation layer. The black matrix has a contact opening above the drain and a color filter containing opening. A color filer layer is formed within the color filter containing opening through inkjet printing. A dielectric layer is formed on the black matrix and the color filter layer. The dielectric layer and the passivation layer are patterned to expose the drain. A pixel electrode electrically connected to the drain is formed.
    Type: Application
    Filed: March 5, 2009
    Publication date: January 7, 2010
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Ta-Wen Liao, Chen-Pang Tung, Chia-Ming Chang, Zong-Long Jhang, Che-Yung Lai, Chun-Yi Chiang, Chou-Huan Yu, Hsiang-Chih Hsiao, Han-Tang Chou, Jun-Kai Chang
  • Publication number: 20100003792
    Abstract: A pixel structure fabricating method is provided. A gate and a gate insulation layer covering the gate are formed on a substrate. A channel layer is formed on the gate insulation layer. A conductive layer is formed on the channel layer and gate insulation layer. A black matrix having a color filer layer accommodating opening is formed on the conductive layer. The black matrix includes a first block and a second block which is thicker than the first block. The conductive layer is patterned with the black matrix as a mask to form a source and a drain on the channel layer. A color filter layer is formed within the color filter layer accommodating opening through inkjet printing. A dielectric layer is formed on the black matrix and color filter layer. The dielectric layer is patterned to expose the drain. A pixel electrode electrically connected to the drain is formed.
    Type: Application
    Filed: October 1, 2008
    Publication date: January 7, 2010
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Che-Yung Lai, Zong-Long Jhang, Chia-Chi Tsai, Chen-Pang Tung, Chia-Ming Chang, Chun-Yi Chiang, Chou-Huan Yu, Hsiang-Chih Hsiao, Han-Tang Chou, Jun-Kai Chang, Ta-Wen Liao
  • Publication number: 20090325331
    Abstract: A method for manufacturing a pixel structure is provided. First, a gate and a gate insulating layer are sequentially formed on the substrate. A channel layer and a second metal layer are sequentially formed on the gate insulating layer. The second metal layer is patterned to form a source and a drain by using a patterned photoresist layer formed thereon, wherein the source and the drain are disposed on a portion of the channel layer. The gate, the channel, the source and the drain form a thin film transistor. A passivation layer is formed on the patterned photoresist layer, the gate insulating layer and the thin film transistor. Then, the patterned photoresist layer is removed, such that the passivation layer thereon is removed simultaneously to form a patterned passivation layer and the drain is exposed. A pixel electrode is formed on the patterned passivation layer and the drain.
    Type: Application
    Filed: September 19, 2008
    Publication date: December 31, 2009
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Chih-Chun Yang, Ming-Yuan Huang, Han-Tu Lin, Chih-Hung Shih, Ta-Wen Liao, Kuo-Lung Fang, Chia-Chi Tsai
  • Patent number: 7629614
    Abstract: A diode disposed on a substrate is provided. The diode includes a semiconductor pattern, a first conductor pattern, a second conductor pattern, an insulating layer, and a top conductor pattern. The first conductor pattern and the second conductor pattern are respectively disposed on a portion of the semiconductor pattern. The insulating layer is disposed on the first conductor layer, the second conductor layer, and the semiconductor pattern. Moreover, the top conductor pattern is disposed on the insulating layer above the semiconductor pattern and electrically connected to the first conductor pattern. In the diode mentioned above, no circuit belonging to the diode is disposed under the semiconductor pattern. Therefore, when the aforementioned diode and other devices are integrated, layout of the devices can adopt the space under the diode.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: December 8, 2009
    Assignee: Au Optronics Corporation
    Inventor: Ta-Wen Liao
  • Patent number: 7598102
    Abstract: A fabricating method for a pixel structure including following procedures is provided. First, a gate and a gate insulator layer are formed sequentially on a substrate. Next, a semiconductor layer, a conductive layer and a photosensitive black matrix having a color filter containing opening are sequentially formed on the gate insulator layer. The photosensitive black matrix includes a first portion and a second portion. A thickness of the first portion is smaller than that of the second portion. A channel, a source and a drain are formed simultaneously using the photosensitive black matrix as a mask. A passivation is formed on the substrate, and a color filer layer is formed within the color filter containing opening via an inkjet printing process and a dielectric layer is formed thereon. Next, a patterning process is applied to expose the drain. Ultimately, a pixel electrode connected to the drain is formed.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: October 6, 2009
    Assignee: Au Optronics Corporation
    Inventors: Chou-Huan Yu, Chun-Yi Chiang, Chia-Chi Tsai, Chen-Pang Tung, Hsiang-Chih Hsiao, Chia-Ming Chang, Zong-Long Jhang, Che-Yung Lai, Han-Tang Chou, Jun-Kai Chang, Ta-Wen Liao
  • Publication number: 20090148972
    Abstract: A method for fabricating a pixel structure includes following steps. First, a substrate is provided. Next, a first conductive layer is formed on the substrate. Next, a first shadow mask is disposed over the first conductive layer. Next, a laser is applied through the first shadow mask to irradiate the first conductive layer to form a gate. Next, a gate dielectric layer is formed on the substrate to cover the gate. After that, a channel layer, a source and a drain are simultaneously formed on the gate dielectric layer over the gate, wherein the gate, the channel layer, the source and the drain together form a thin film transistor. A patterned passivation layer is formed on the thin film transistor and the patterned passivation layer exposes a part of the drain. Furthermore, a pixel electrode electrically connecting to the drain is formed.
    Type: Application
    Filed: April 18, 2008
    Publication date: June 11, 2009
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Kuo-Lung Fang, Chih-Chun Yang, Ming-Yuan Huang, Han-Tu Lin, Chih-Hung Shih, Ta-Wen Liao, Shiun-Chang Jan, Chia-Chi Tsai
  • Publication number: 20090148987
    Abstract: A method for fabricating a pixel structure is disclosed. A substrate is provided. A first conductive layer is formed on the substrate, and a first shadow mask exposing a portion of the first conductive layer is disposed over the first conductive layer. Laser is used to irradiate the first conductive layer for removing the part of the first conductive layer and forming a gate. A gate dielectric layer is formed on the substrate to cover the gate. A channel layer is formed on the gate dielectric layer over the gate. A source and a drain are formed on the channel layer and respectively above both sides of the gate. A patterned passivation layer is formed to cover the channel layer and expose the drain. An electrode material layer is formed to cover the patterned passivation layer and the exposed drain.
    Type: Application
    Filed: April 18, 2008
    Publication date: June 11, 2009
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Ta-Wen Liao, Chih-Chun Yang, Ming-Yuan Huang, Han-Tu Lin, Chih-Hung Shih, Chin-Yueh Liao, Chia-Chi Tsai
  • Publication number: 20090087954
    Abstract: A method for fabricating a pixel structure using a laser ablation process is provided. This fabrication method forms a gate, a channel layer, a source, a drain, a passivation layer, and a pixel electrode sequentially by using a laser ablation process. Particularly, the fabrication method is not similar to a photolithography and etching process, so as to reduce the complicated photolithography and etching processes, such as spin coating process, soft-bake, hard-bake, exposure, developing, etching, and stripping. Therefore, the fabrication method simplifies the process and thus reduces the fabrication cost.
    Type: Application
    Filed: January 22, 2008
    Publication date: April 2, 2009
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Han-Tu Lin, Chih-Chun Yang, Ming-Yuan Huang, Chih-Hung Shih, Ta-Wen Liao, Chia-Chi Tsai
  • Patent number: 7507612
    Abstract: A flat panel display and fabrication method thereof. The present invention uses four etching processes to define a second conducting layer, a doped semiconductor layer and a semiconductor layer. The first etching process is a wet etching using a first resist layer to etch the second conducting layer. The second etching process is executed with an etchant comprising oxygen to etch the doped semiconductor layer and the semiconductor layer, and the first resist layer undergoes ashing during etching so as to become a second resist layer with a channel pattern. The third etching process is another wet etching, and the second conducting layer is etched again using the second resist layer as the etching mask. The fourth etching process is executed to dry etch the doped semiconductor layer using the second resist layer as the etching mask.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: March 24, 2009
    Assignee: AU Optronics Corp.
    Inventors: Han-Chung Lai, Ta-Wen Liao
  • Publication number: 20090068777
    Abstract: A method for manufacturing a pixel structure is provided. First, a substrate with a gate formed thereon is provided. Next, a gate dielectric layer covering the gate is formed on the substrate. Then, a channel layer, a source and a drain are formed on the gate dielectric layer over the gate. The source and the drain are disposed on a portion of the channel layer. The gate, the channel layer, the source and the drain constitute a thin film transistor. Then, a passivation layer is formed on the gate dielectric layer and the thin film transistor. After that, a laser beam is utilized to irradiate the passivation layer via a first shadow mask so as to remove a portion of the passivation layer for exposing the drain. Then, a pixel electrode is formed on the gate dielectric layer and connected to the exposed drain.
    Type: Application
    Filed: May 15, 2008
    Publication date: March 12, 2009
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Shiun-Chang Jan, Chih-Chun Yang, Ming-Yuan Huang, Han-Tu Lin, Chih-Hung Shih, Ta-Wen Liao, Chia-Chi Tsai
  • Publication number: 20090053861
    Abstract: A method for fabricating a pixel structure is provided. A substrate is provided, and a gate is formed on the substrate. A gate dielectric layer covering the gate is formed on the substrate. A semiconductor layer is formed on the gate dielectric layer. A first shadow mask exposing parts of the semiconductor layer is provided above the semiconductor layer. A laser is irradiated on the semiconductor layer through the first shadow mask to remove parts of semiconductor layer and form a channel layer. A source and a drain are respectively formed on the channel layer at both sides of the gate. A patterned passivation layer which covers the channel layer and exposes the drain is formed. A conductive layer is formed to cover the patterned passivation layer and the drain. The conductive layer is automatically patterned by the patterned passivation layer to form a pixel electrode.
    Type: Application
    Filed: March 2, 2008
    Publication date: February 26, 2009
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Chin-Yueh Liao, Chih-Chun Yang, Ming-Yuan Huang, Han-Tu Lin, Chih-Hung Shih, Ta-Wen Liao, Chia-Chi Tsai