Abstract: A vehicle electronic device and a storage method therefore are provided. The vehicle electronic device includes a display unit, a motor driving assembly and a workbench. The motor driving assembly is connected to the display unit. An accommodating space with an opening is formed inside the workbench. The motor driving assembly moves and flips the display unit, so that the display unit is displayed on a surface of the workbench or accommodated in the accommodating space.

Abstract: The present disclosure is directed to methods for the fabrication of buried layers in gate-all-around (GAA) transistor structures to suppress junction leakage. In some embodiments, the method includes forming a doped epitaxial layer on a substrate, forming a stack of alternating first and second nano-sheet layers on the epitaxial layer, and patterning the stack and the epitaxial layer to form a fin structure. The method includes forming a sacrificial gate structure on the fin structure, removing portions of the fin structure not covered by the sacrificial gate structure, and etching portions of the first nano-sheet layers. Additionally, the method includes forming spacer structures on the etched portions of the first nano-sheet layers and forming source/drain (S/D) epitaxial structures on the epitaxial layer abutting the second nano-sheet layers.

Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

Abstract: A resonant flyback power converter includes: a first and a second transistors which form a half-bridge circuit for switching a transformer and a resonant capacitor to generate an output voltage; a current-sense device for sensing a switching current of the half-bridge circuit to generate a current-sense signal; and a switching control circuit generating a first and a second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal controls the half-bridge circuit to generate a positive current to magnetize the transformer and charge the resonant capacitor. The turn-on of the second driving signal controls the half-bridge circuit to generate a negative current to discharge the resonant capacitor. The switching control circuit turns off the first transistor when the positive current exceeds a positive-over-current threshold, and/or, turns off the second transistor when the negative current exceeds a negative-over-current threshold.

Abstract: A switching converter circuit for switching one end of an inductor therein between plural voltages according to a pulse width modulation (PWM) signal to convert an input voltage to an output voltage. The switching converter circuit has a driver circuit including a high side driver, a low side driver, a high side sensor circuit, and a low side sensor circuit. The high side sensor circuit is configured to sense a gate-source voltage of a high side metal oxide semiconductor field effect transistor (MOSFET), to generate a low side enable signal for enabling the low side driver to switch a low side MOSFET according to the PWM signal. The low side sensor circuit is configured to sense a gate-source voltage of a low side MOSFET, to generate a high side enable signal for enabling the high side driver to switch a high side MOSFET according to the PWM signal.

Abstract: Disclosed is an earphone system. The earphone system includes a charging box and an earphone, which is detachably assembled in the charging box. The charging box includes a processing module provided with a first identification time period, a power outputting module and a first switch module. During the first identification time period when the earphone is connected to the charging box, the earphone system is in a test mode, and the first switch module is switched for the charging box to transmit power to the earphone through the power outputting module and the first switch module. After the earphone is connected to the charging box for more than the first identification time period, the earphone system is in a communication mode, and the first switch module is switched for the charging box to transmit a data signal to the earphone through the processing module and the first switch module.

Abstract: Disclosed is an earphone system. The earphone system includes a charging box and an earphone, which is detachably assembled in the charging box. The charging box includes a processing module provided with a first identification time period, a power outputting module and a first switch module. During the first identification time period when the earphone is connected to the charging box, the earphone system is in a test mode, and the first switch module is switched for the charging box to transmit power to the earphone through the power outputting module and the first switch module. After the earphone is connected to the charging box for more than the first identification time period, the earphone system is in a communication mode, and the first switch module is switched for the charging box to transmit a data signal to the earphone through the processing module and the first switch module.

Abstract: One aspect of this description relates to a memory array. In some embodiments, the memory array includes a first memory cell coupled between a first local select line and a first local bit line, a second memory cell coupled between a second local select line and a second local bit line, a first switch coupled to a global bit line, a second switch coupled between the first local bit line and the first switch, and a third switch coupled between the second local select line and the first switch.

Abstract: A semiconductor structure includes semiconductor layers disposed over a substrate and oriented lengthwise in a first direction, a metal gate stack disposed over the semiconductor layers and oriented lengthwise in a second direction perpendicular to the first direction, where the metal gate stack includes a top portion and a bottom portion that is interleaved with the semiconductor layers, source/drain features disposed in the semiconductor layers and adjacent to the metal gate stack, and an isolation structure protruding from the substrate, where the isolation structure is oriented lengthwise along the second direction and spaced from the metal gate stack along the first direction, and where the isolation structure includes a dielectric layer and an air gap.

Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: The present disclosure is directed to methods for the fabrication of buried layers in gate-all-around (GAA) transistor structures to suppress junction leakage. In some embodiments, the method includes forming a doped epitaxial layer on a substrate, forming a stack of alternating first and second nano-sheet layers on the epitaxial layer, and patterning the stack and the epitaxial layer to form a fin structure. The method includes forming a sacrificial gate structure on the fin structure, removing portions of the fin structure not covered by the sacrificial gate structure, and etching portions of the first nano-sheet layers. Additionally, the method includes forming spacer structures on the etched portions of the first nano-sheet layers and forming source/drain (S/D) epitaxial structures on the epitaxial layer abutting the second nano-sheet layers.

Abstract: A semiconductor structure includes semiconductor layers disposed over a substrate and oriented lengthwise in a first direction, a metal gate stack disposed over the semiconductor layers and oriented lengthwise in a second direction perpendicular to the first direction, where the metal gate stack includes a top portion and a bottom portion that is interleaved with the semiconductor layers, source/drain features disposed in the semiconductor layers and adjacent to the metal gate stack, and an isolation structure protruding from the substrate, where the isolation structure is oriented lengthwise along the second direction and spaced from the metal gate stack along the first direction, and where the isolation structure includes a dielectric layer and an air gap.

Abstract: A vehicle shifting mechanism includes a gearbox, a shift drive unit and a gearshift lever. Through electrical connection between a control switch and the shift drive unit, the operation of controlling the forward or reverse gear is carried out, so that the shift drive unit drives the gearshift lever to produce the action of pushing down the gear or pushing up the gear. Through an automatic shift switch and in cooperation with a main driving control processor, when the automatic shift switch is turned into automatic shift mode, the main driving control processor receives the data of the main power motor or the engine speed and torque load of the vehicle to activate the shift drive unit to drive the gearshift lever to generate a fully automatic downshifting gear or an upshifting gear and a neutral gear control.

Abstract: The present invention provides a cleaning method and equipment thereof for object FOUP, comprising the following steps: firstly separating the object FOUP into a container lid and a container body, then conducting individual processes of wet washing, liquid removing and vacuum drying for the container lid and container body, and in the end combining the container lid and container body to complete the cleaning procedure of the object FOUP; specifically, during the liquid removing process, multiple wind knives are used to carry out liquid removing for the container body, and during the vacuum drying process after liquid removing, multiple thermal components are used to carry out vacuum drying for the container body under a vacuum environment; moreover, the present invention also includes the cleaning equipment to execute the above method, for the purpose of overcoming the problem that the wet cleaning process in the conventional automatic chip FOUP cleaning technique cannot effectively clean object FOUPs with

Abstract: Various embodiments of the present disclosure provide a memory device and methods of forming the same. In one embodiment, a memory device is provided. The memory device includes a gate electrode disposed in an insulating material layer, a ferroelectric dielectric layer disposed over the gate electrode, a metal oxide semiconductor layer disposed over the ferroelectric dielectric layer, a source feature disposed over the metal oxide semiconductor layer, wherein the source feature has a first dimension, and a source extension. The source extension includes a first portion disposed over the source feature, wherein the first portion has a second dimension that is greater than the first dimension. The source extension also includes a second portion extending downwardly from the first portion to an elevation that is lower than a top surface of the source feature.

Abstract: A method for treating high aspect ratio (HAR) structures arranged on a surface of a substrate includes a) spin rinsing the surface of the substrate using a first rinsing liquid; b) spinning off the first rinsing liquid from the surface of the substrate; and c) directing a gas mixture containing hydrogen fluoride onto the surface of the substrate after the first rinsing liquid is dispensed.

Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

Abstract: A chip deviation correction method for maskless exposure machines includes the steps of calculating the bonding positions of chips on a substrate to define the coordinates of the chips on the substrate, creating a separating boundary among the chips according to the coordinates of the chips on the substrate to form plural of bonding areas for accommodating the chips, calculating a lead wire of the chips in the bonding area and a compensating wire which spans across the separating boundary between each lead wire and the lead wire of the corresponding adjacent chip according to the calculated lead wire; and forming a digital exposed layer according to each of the lead wires and each of the compensating wires.

Abstract: The disclosure provides a charging device and a method for positioning an electronic device. The method includes: in response to determining that a positioning request signal from an electronic device is received, enabling multiple antennas; controlling each antenna to receive a first radio frequency signal broadcast by the electronic device, and determining an arrival angle of the first radio frequency signal and a distance between the electronic device and the charging device based on the first radio frequency signal received by each antenna; and determining a relative position between the charging device and the electronic device based on the arrival angle and distance.