Abstract: Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.

Abstract: Disclosed is an earphone system. The earphone system includes a charging box and an earphone, which is detachably assembled in the charging box. The charging box includes a processing module provided with a first identification time period, a power outputting module and a first switch module. During the first identification time period when the earphone is connected to the charging box, the earphone system is in a test mode, and the first switch module is switched for the charging box to transmit power to the earphone through the power outputting module and the first switch module. After the earphone is connected to the charging box for more than the first identification time period, the earphone system is in a communication mode, and the first switch module is switched for the charging box to transmit a data signal to the earphone through the processing module and the first switch module.

Abstract: Disclosed is an earphone system. The earphone system includes a charging box and an earphone, which is detachably assembled in the charging box. The charging box includes a processing module provided with a first identification time period, a power outputting module and a first switch module. During the first identification time period when the earphone is connected to the charging box, the earphone system is in a test mode, and the first switch module is switched for the charging box to transmit power to the earphone through the power outputting module and the first switch module. After the earphone is connected to the charging box for more than the first identification time period, the earphone system is in a communication mode, and the first switch module is switched for the charging box to transmit a data signal to the earphone through the processing module and the first switch module.

Abstract: A memory device includes first transistor over a semiconductor substrate, wherein the first transistor includes a first word line extending over the semiconductor substrate; a second transistor over the semiconductor substrate, wherein the second transistor includes a second word line extending over the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along and contacting the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is between the bit line and the word line; and an isolation region between the source line and the bit line.

Abstract: A semiconductor structure includes fins protruding from a substrate and separated by a dielectric layer, each semiconductor fin including a plurality of semiconductor layers, source/drain (S/D) features disposed in the semiconductor fins, a first metal gate stack and a second metal gate stack disposed over the semiconductor fins and adjacent to the S/D features, where the first and the second metal gate stacks each include a top portion and a bottom portion disposed below the top portion, and where the bottom portion is interleaved with the semiconductor layers, and an isolation feature disposed on the dielectric layer and in contact with a sidewall surface of each of the first and the second metal gate stacks, where the isolation feature protrudes from the top portion of the first and the second metal gate stack, and where the isolation feature includes two compositionally different dielectric layers.

Abstract: A gel-time detection apparatus includes a carrier, a stirring device, and an image-capturing device. The gel-time detection apparatus uses the carrier to liquefied powder to be detected, uses the stirring device to stir the liquefied powder and sense the torque of stirring the liquefied powder, and uses the image-capturing device to capture images of the liquefied powder, so as to determine a gel time according to a determination criterion relevant to the torque and the images. A gel-time detection method includes liquefying powder to be detected, stirring the powder, sensing the torque of stirring the liquefied powder, capturing images of the liquefied powder, and then determining a gel time according to a determination criterion relevant to the torque and the images. The determination criterion may include a torque predetermined threshold and an area-shrinkage-rate predetermined threshold.

Abstract: Disclosed is an earphone system. The earphone system includes a charging box and an earphone, which is detachably assembled in the charging box. The charging box includes a processing module provided with a first identification time period, a power outputting module and a first switch module. During the first identification time period when the earphone is connected to the charging box, the earphone system is in a test mode, and the first switch module is switched for the charging box to transmit power to the earphone through the power outputting module and the first switch module. After the earphone is connected to the charging box for more than the first identification time period, the earphone system is in a communication mode, and the first switch module is switched for the charging box to transmit a data signal to the earphone through the processing module and the first switch module.

Abstract: Embodiments of the present disclosure provide a side-channel dynamic random access memory (DRAM) cell and cell array that utilizes a vertical design with side channel transistors. A dielectric layer disposed over a substrate. A gate electrode is embedded in the dielectric layer. A channel layer wraps the gate electrode and a conductive structure is adjacent to the channel layer, with the channel layer interposed between the gate electrode and the conductive structure. The semiconductor structure also includes a dielectric structure disposed over the conductive structure and the gate electrode, the channel layer extending up through the dielectric structure.

Abstract: The present disclosure is directed to methods for the fabrication of buried layers in gate-all-around (GAA) transistor structures to suppress junction leakage. In some embodiments, the method includes forming a doped epitaxial layer on a substrate, forming a stack of alternating first and second nano-sheet layers on the epitaxial layer, and patterning the stack and the epitaxial layer to form a fin structure. The method includes forming a sacrificial gate structure on the fin structure, removing portions of the fin structure not covered by the sacrificial gate structure, and etching portions of the first nano-sheet layers. Additionally, the method includes forming spacer structures on the etched portions of the first nano-sheet layers and forming source/drain (S/D) epitaxial structures on the epitaxial layer abutting the second nano-sheet layers.

Abstract: A sound transmission device includes a main body, a first magnetic member, and a cover assembly. The main body includes a sound transmission opening. The first magnetic member is fixed to the main body and is adjacent to the sound transmission opening. The cover assembly includes an outer cover, a second magnetic member, and a fixing member. The second magnetic member is fixed between the outer cover and the fixing member. The cover assembly is magnetically attached to the first magnetic member through the second magnetic member, so that the outer cover covers the sound transmission opening. The outer cover includes a through hole, and the through hole is in communication with the sound transmission opening.

Abstract: A semiconductor structure includes semiconductor layers disposed over a substrate and oriented lengthwise in a first direction, a metal gate stack disposed over the semiconductor layers and oriented lengthwise in a second direction perpendicular to the first direction, where the metal gate stack includes a top portion and a bottom portion that is interleaved with the semiconductor layers, source/drain features disposed in the semiconductor layers and adjacent to the metal gate stack, and an isolation structure protruding from the substrate, where the isolation structure is oriented lengthwise along the second direction and spaced from the metal gate stack along the first direction, and where the isolation structure includes a dielectric layer and an air gap.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a 3D metal insulator metal (MIM) capacitor structure with an increased capacitance per unit area in a semiconductor structure. The MIM structure includes a substrate, an oxide layer formed over the substrate, and a first metal layer formed over the oxide layer. The first metal layer includes a plurality of mandrels formed on a surface of the first metal layer. The MIM structure also includes a dielectric layer formed over the first metal layer and the plurality of mandrels, a second metal layer formed over on the dielectric layer, and one or more interconnect structures electrically connected to the first and second metal layers.

Abstract: The disclosure provides a charging device and a method for positioning an electronic device. The method includes: in response to determining that a positioning request signal from an electronic device is received, enabling multiple antennas; controlling each antenna to receive a first radio frequency signal broadcast by the electronic device, and determining an arrival angle of the first radio frequency signal and a distance between the electronic device and the charging device based on the first radio frequency signal received by each antenna; and determining a relative position between the charging device and the electronic device based on the arrival angle and distance.

Abstract: The present invention provides a cleaning method and equipment thereof for object FOUP, comprising the following steps: firstly separating the object FOUP into a container lid and a container body, then conducting individual processes of wet washing, liquid removing and vacuum drying for the container lid and container body, and in the end combining the container lid and container body to complete the cleaning procedure of the object FOUP; specifically, during the liquid removing process, multiple wind knives are used to carry out liquid removing for the container body, and during the vacuum drying process after liquid removing, multiple thermal components are used to carry out vacuum drying for the container body under a vacuum environment; moreover, the present invention also includes the cleaning equipment to execute the above method, for the purpose of overcoming the problem that the wet cleaning process in the conventional automatic chip FOUP cleaning technique cannot effectively clean object FOUPs with

Abstract: A semiconductor structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure. The structure also includes an inter-layer dielectric (ILD) structure formed over the gate structure. The structure also includes a contact blocking structure formed through the ILD structure over the source/drain epitaxial structure. A lower portion of the contact blocking structure is surrounded by an air gap, and the air gap is covered by a portion of the ILD structure.

Abstract: A memory device includes a three dimensional memory array having memory cells arranged on multiple floors in rows and columns. Each column is associated with a bit line and a select line. The memory device further includes select gate pairs each being associated with a column. The bit line of a column is connectable to a corresponding a global bit line through a first select gate of a select gate pair associated with the column and a select line of the column is connectable to a corresponding global select line through the second select gate of the select gate pair associated with the column. The plurality of select gate pairs are formed in a different layer than the plurality of memory cells.

Abstract: A rotation mechanism includes a base, a rotation plate, and an elastic element. The base has two base side walls opposite to each other, an accommodation space between the two base side walls, an abutting portion, and two pivot portions opposite to each other. The abutting portion is located at one end of the base side walls, and the pivot portions are respectively located at the other end of the base side walls. The rotation plate is pivotally connected to the base and between the pivot portions. The elastic element has a first pivot section, an elastic bending section, and a second pivot section that are sequentially connected to each other. The first pivot section is pivotally connected to the two base side walls, and the second pivot section is pivotally connected to one side of the rotation plate.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a 3D metal insulator metal (MIM) capacitor structure with an increased capacitance per unit area in a semiconductor structure. The MIM structure includes a substrate, an oxide layer formed over the substrate, and a first metal layer formed over the oxide layer. The first metal layer includes a plurality of mandrels formed on a surface of the first metal layer. The MIM structure also includes a dielectric layer formed over the first metal layer and the plurality of mandrels, a second metal layer formed over on the dielectric layer, and one or more interconnect structures electrically connected to the first and second metal layers.

Abstract: Disclosed is an earphone system. The earphone system includes a charging box and an earphone, which is detachably assembled in the charging box. The charging box includes a processing module provided with a first identification time period, a power outputting module and a first switch module. During the first identification time period when the earphone is connected to the charging box, the earphone system is in a test mode, and the first switch module is switched for the charging box to transmit power to the earphone through the power outputting module and the first switch module. After the earphone is connected to the charging box for more than the first identification time period, the earphone system is in a communication mode, and the first switch module is switched for the charging box to transmit a data signal to the earphone through the processing module and the first switch module.

Abstract: A semiconductor structure includes semiconductor layers disposed over a substrate and oriented lengthwise in a first direction, a metal gate stack disposed over the semiconductor layers and oriented lengthwise in a second direction perpendicular to the first direction, where the metal gate stack includes a top portion and a bottom portion that is interleaved with the semiconductor layers, source/drain features disposed in the semiconductor layers and adjacent to the metal gate stack, and an isolation structure protruding from the substrate, where the isolation structure is oriented lengthwise along the second direction and spaced from the metal gate stack along the first direction, and where the isolation structure includes a dielectric layer and an air gap.