Abstract: Disclosed is a method for performing reliability qualification of manufactured integrated circuit (IC) chips. In the method, IC chips are manufactured according to a design and sorted into groups, which correspond to different process windows within a process distribution for the design. Group fail rates are determined for the groups. Reliability qualification of the manufactured IC chips is performed. Specifically, a sample of the IC chips is stress tested and the manufactured IC chips are qualified if the actual fail rate of the sample is no greater than an expected fail rate. The expected fail rate used is not, however, the expected overall fail rate for all the manufactured IC chips. Instead it is a unique expected fail rate for the specific sample itself and it is determined considering fail rate contributions from only those specific groups of IC chips from which the IC chips in the sample were selected.

Abstract: A computer-implemented method for evaluating a circuit design to protect a plurality of metal connections from current pulse damage, the method includes receiving a circuit design including the plurality of metal connections and evaluating a maximum peak current of one or more of the plurality of metal connections. The method further includes determining a peak current threshold for the plurality of metal connections based on physical characteristics of the plurality of metal connection and responsive to determining that the maximum peak current of the one or more of the plurality of metal connections exceeds the peak current threshold, performing a peak current design modification to modify the plurality of metal connections in the circuit design.

Abstract: Embodiments of the invention provide a method, system, and program product for predicting a delay of a critical path. In one embodiment, the invention provides a method of predicting a delay of at least one critical path of an integrated circuit, the method comprising: determining a delay of at least one ring oscillator on the integrated circuit; and calculating a predicted delay for the at least one critical path delay based on a delay of components of the critical path at a corner condition, a wire delay of the at least one critical path, a delay of the at least one ring oscillator at a corner condition, and the determined delay of the at least one ring oscillator.

Abstract: Disclosed are a chip performance monitoring system, method and a computer program product, wherein a performance monitor output signal is propagated through an adjacent scan chain to avoid signal degradation incident to across-chip transmission of high frequency signals. Since the clock signal frequency used to control signal propagation through the scan chain will typically be less than twice the performance monitor output signal frequency, frequency sub-sampling with aliasing occurs. To compensate, signal propagation through the scan chain can be controlled during different time periods using different clock signals having different clock signal frequencies and, during these different time periods, different data outputs can be captured at an output node of the scan chain. The data output frequencies of these different data outputs can be measured and the performance monitor output signal frequency can be determined based on the different data output frequencies given the different clock signal frequencies.

Abstract: Method of burn-in power optimization which includes: testing integrated circuit devices to record a performance speed for each of the integrated circuit devices; categorizing each integrated circuit device by a selective voltage binning (SVB) process into a voltage bin according to the performance speed of the integrated circuit device; performing a burn-in operation on each of the integrated circuit devices while toggling an SVB performance monitor on each of the integrated circuit devices; testing the plurality of integrated circuit devices after the burn-in operation; categorizing each integrated circuit device into the SVB voltage bin according to the performance speed of the integrated circuit device after the burn-in operation; when the SVB voltage bin after the burn-in operation corresponds to an SVB voltage bin having a slower performance speed than before the burn-in operation, changing the SVB voltage bin to the slower performance speed.

Abstract: Disclosed is a method for performing reliability qualification of manufactured integrated circuit (IC) chips. In the method, IC chips are manufactured according to a design and sorted into groups, which correspond to different process windows within a process distribution for the design. Group fail rates are determined for the groups. Reliability qualification of the manufactured IC chips is performed. Specifically, a sample of the IC chips is stress tested and the manufactured IC chips are qualified if the actual fail rate of the sample is no greater than an expected fail rate. The expected fail rate used is not, however, the expected overall fail rate for all the manufactured IC chips. Instead it is a unique expected fail rate for the specific sample itself and it is determined considering fail rate contributions from only those specific groups of IC chips from which the IC chips in the sample were selected.

Abstract: Disclosed is a method for performing reliability qualification of manufactured integrated circuit (IC) chips. In the method, IC chips are manufactured according to a design and sorted into groups, which correspond to different process windows within a process distribution for the design. Group fail rates are determined for the groups. Reliability qualification of the manufactured IC chips is performed. Specifically, a sample of the IC chips is stress tested and the manufactured IC chips are qualified if the actual fail rate of the sample is no greater than an expected fail rate. The expected fail rate used is not, however, the expected overall fail rate for all the manufactured IC chips. Instead it is a unique expected fail rate for the specific sample itself and it is determined considering fail rate contributions from only those specific groups of IC chips from which the IC chips in the sample were selected.

Abstract: Disclosed is an integrated circuit (IC) chip having an on-chip usable life depletion meter. This meter incorporates programmable bits, which represent units of usable life. These programmable bits are sequentially ordered from an initial programmable bit to a last programmable bit and are automatically programmed in order, as the expected usable life of the IC chip is depleted. These programmable bits are readable to determine the remaining usable life of the IC chip. Also disclosed is a method that uses the on-chip usable life depletion meter. In the method, the remaining usable life of an IC chip, once known, is used either as the basis for allowing re-use of the IC chip (e.g., for a non-critical application and when the remaining usable life is sufficient) or as the basis for preventing re-use of the IC chip (e.g., for a critical application or when the remaining usable life is insufficient).

Abstract: Disclosed herein are methods for making integrated circuit (IC) chip reliability estimations based on resistance measurements and for using such estimations to disposition manufactured chips. In the methods, a resistance-to-electromigration fail rate correlation can be empirically determined for an integrated circuit chip design. Additionally, for each chip manufactured according to the design, at least one resistance monitor can be used to acquire a resistance value for that manufactured chip. Then, given the resistance value and the resistance-to-electromigration fail rate correlation, the expected reliability of the manufactured chip can be estimated and the manufactured chip can be dispositioned in a variety of different ways.

Abstract: A computer-implemented method for evaluating a circuit design to protect a plurality of metal connections from current pulse damage, the method includes receiving a circuit design including the plurality of metal connections and evaluating a maximum peak current of one or more of the plurality of metal connections. The method further includes determining a peak current threshold for the plurality of metal connections based on physical characteristics of the plurality of metal connection and responsive to determining that the maximum peak current of the one or more of the plurality of metal connections exceeds the peak current threshold, performing a peak current design modification to modify the plurality of metal connections in the circuit design.

Abstract: Method of burn-in power optimization which includes: testing integrated circuit devices to record a performance speed for each of the integrated circuit devices; categorizing each integrated circuit device by a selective voltage binning (SVB) process into a voltage bin according to the performance speed of the integrated circuit device; performing a burn-in operation on each of the integrated circuit devices while toggling an SVB performance monitor on each of the integrated circuit devices; testing the plurality of integrated circuit devices after the burn-in operation; categorizing each integrated circuit device into the SVB voltage bin according to the performance speed of the integrated circuit device after the burn-in operation; when the SVB voltage bin after the burn-in operation corresponds to an SVB voltage bin having a slower performance speed than before the burn-in operation, changing the SVB voltage bin to the slower performance speed.

Abstract: Disclosed are methods for improving integrated circuit (IC) chip reliability. IC chips are manufactured and sorted into groups corresponding to process windows within a process distribution for the design. Group fail rates are set for each group based on failure mechanism fail rates, which are set for multiple failure mechanisms. An overall fail rate is determined for the full process distribution based on the group fail rates. First contribution amounts of the groups to the overall fail rate and second contribution amounts of the failure mechanisms to the group fail rate of each group are determined. Based on an analysis of the contribution amounts, at least one specific failure mechanism is selected and targeted for improvement (i.e., changes directed to the specific failure mechanism(s) are proposed and implemented). Optionally, proposed change(s) are only implemented if they will be sufficient to meet a reliability requirement and/or will not be cost-prohibitive.

Abstract: Aspects of the present disclosure include a computer-implemented method for identifying an operating temperature of an integrated circuit (IC), the method including using a computing device for: applying a test voltage to a test circuit embedded within the IC, the test circuit including a phase shift memory (PSM) element therein, wherein the PSM element crystallizes at a crystallization temperature from an amorphous phase having a first electrical resistance into a crystalline phase having a second electrical resistance, the second electrical resistance being less than the first electrical resistance; and identifying the IC as having operated above the crystallization temperature in response to a resistance of the test circuit at the test voltage being outside of the target operating range.

Abstract: In the systems and methods, an identifier is generated for a printed circuit board (PCB), chips are connected to the PCB, and corresponding sets of programmable bits on the chips are programmed to match specific sections of the identifier. Due to the generation of the identifier and the programming of the corresponding sets of programmable bits on the chips to match specific sections of the identifier, the validity of the chips can be verified at any time during product life. For example, for each chip, its set of programmable bits can be read and, then, a determination can be made as to whether that set of programmable bits is indeed programmed to match a specific section of the identifier. Operation of the PCB can be allowed when all the chips are determined to be valid and prohibited when any of the chips are determined to be invalid (e.g., previously used).

Abstract: Disclosed is a method for performing reliability qualification of manufactured integrated circuit (IC) chips. In the method, IC chips are manufactured according to a design and sorted into groups, which correspond to different process windows within a process distribution for the design. Group fail rates are determined for the groups. Reliability qualification of the manufactured IC chips is performed. Specifically, a sample of the IC chips is stress tested and the manufactured IC chips are qualified if the actual fail rate of the sample is no greater than an expected fail rate. The expected fail rate used is not, however, the expected overall fail rate for all the manufactured IC chips. Instead it is a unique expected fail rate for the specific sample itself and it is determined considering fail rate contributions from only those specific groups of IC chips from which the IC chips in the sample were selected.

Abstract: Disclosed are methods for improving integrated circuit (IC) chip reliability. IC chips are manufactured and sorted into groups corresponding to process windows within a process distribution for the design. Group fail rates are set for each group based on failure mechanism fail rates, which are set for multiple failure mechanisms. An overall fail rate is determined for the full process distribution based on the group fail rates. First contribution amounts of the groups to the overall fail rate and second contribution amounts of the failure mechanisms to the group fail rate of each group are determined. Based on an analysis of the contribution amounts, at least one specific failure mechanism is selected and targeted for improvement (i.e., changes directed to the specific failure mechanism(s) are proposed and implemented). Optionally, proposed change(s) are only implemented if they will be sufficient to meet a reliability requirement and/or will not be cost-prohibitive.

Abstract: Disclosed is a method for improving integrated circuit (IC) chip reliability. In the method, IC chips, which are manufactured according to a given IC chip design, are sorted into multiple different groups associated with different process windows in the process distribution for the design. Different operating voltages are assigned to the different groups, respectively, in order to optimize overall reliability of IC chips across the process distribution. That is, each group is associated with a specific process window, comprises a specific portion of the IC chips and is assigned a group-specific operating voltage that minimizes the fail rate of the specific portion of the IC chips and that, thereby optimizes the reliability of the specific portion of the IC chips. The group-specific operating voltage will be within minimum and maximum voltages associated with either the process distribution or the specific process window (e.g., following power-optimized selective voltage binning).

Abstract: Disclosed is an integrated circuit (IC) chip having an on-chip usable life depletion meter. This meter incorporates programmable bits, which represent units of usable life. These programmable bits are sequentially ordered from an initial programmable bit to a last programmable bit and are automatically programmed in order, as the expected usable life of the IC chip is depleted. These programmable bits are readable to determine the remaining usable life of the IC chip. Also disclosed is a method that uses the on-chip usable life depletion meter. In the method, the remaining usable life of an IC chip, once known, is used either as the basis for allowing re-use of the IC chip (e.g., for a non-critical application and when the remaining usable life is sufficient) or as the basis for preventing re-use of the IC chip (e.g., for a critical application or when the remaining usable life is insufficient).

Abstract: In the systems and methods, an identifier is generated for a printed circuit board (PCB), chips are connected to the PCB, and corresponding sets of programmable bits on the chips are programmed to match specific sections of the identifier. Due to the generation of the identifier and the programming of the corresponding sets of programmable bits on the chips to match specific sections of the identifier, the validity of the chips can be verified at any time during product life. For example, for each chip, its set of programmable bits can be read and, then, a determination can be made as to whether that set of programmable bits is indeed programmed to match a specific section of the identifier. Operation of the PCB can be allowed when all the chips are determined to be valid and prohibited when any of the chips are determined to be invalid (e.g., previously used).

Abstract: Aspects of the present disclosure include a computer-implemented method for identifying an operating temperature of an integrated circuit (IC), the method including using a computing device for: applying a test voltage to a test circuit embedded within the IC, the test circuit including a phase shift memory (PSM) element therein, wherein the PSM element crystallizes at a crystallization temperature from an amorphous phase having a first electrical resistance into a crystalline phase having a second electrical resistance, the second electrical resistance being less than the first electrical resistance; and identifying the IC as having operated above the crystallization temperature in response to a resistance of the test circuit at the test voltage being outside of the target operating range.