Abstract: An address conversion method and unit for a data processing system is disclosed which converts logical addresses into physical addresses representative of plural addressable storage locations. Each instruction includes a portion indicative of a first or second kind of instruction. In the case where an instruction is of the first kind, the content of a register in a first base register arrangement specified by the instruction is added with an address part of the instruction to produce a logical address. In the case where an instruction is of the second kind, on the other hand, the content of a register in a second base register arrangement specified by the instruction different from the first base register arrangement is juxtaposed with an address part of the instruction to produce a logical address.

Abstract: In an electronic computer system wherein, when a microprogram-controlled central processing unit receives a stop signal from a console, the contents of a group of registers are assigned to predetermined fixed areas in a main memory and, in response to a start signal, the assigned contents of the group of registers are delivered from the fixed areas to the group of registers. The reading and writing of the contents of the group of registers within the central processing unit is effected for the fixed areas of the main memory in which the contents are assigned.

Abstract: In a multi-computer system having input/output devices for common use, protection is made for the devices upon transferring of the input/output data by comparing a device identifying number or address signal and a number signal identifying a central processor unit which demands the transfer of data, thereby to determine on the basis of the result of the comparison whether the data transfer between the device and the central processor unit is allowable. When the transfer is not admitted, the input/output operation of the device is inhibited.

Abstract: A bus-coupler or bus window in an information transport system for connecting a plurality of buses, to each of which a plurality of arithmetic units, a plurality of memory or storage units and a plurality of input-output units are connected separately through stations. The bus coupler includes a dead-lock control circuit for preventing a dead-lock which could possibly occur in communication between the buses.