Patents by Inventor Tadanori Yamada
Tadanori Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160365298Abstract: In a semiconductor device, an insulating substrate housed in an housing opening portion of a resin case includes an insulating board, a first metal layer formed on the upper surface of the insulating board, a second metal layer which is formed on an outer peripheral edge portion of the upper surface of the insulating board and is in contact with a level difference portion, and a third metal layer formed on the under surface of the insulating board and leveled with or protruding from the under surface of the resin case. The first and second metal layers are formed by etching copper foil formed on the insulating board so that these metal layers have the same thickness. The thickness of the second metal layer may be changed relatively freely according to the housing depth of the resin case. Thus, the semiconductor device may be made thin.Type: ApplicationFiled: May 10, 2016Publication date: December 15, 2016Applicant: FUJI ELECTRIC CO., LTD.Inventor: Tadanori YAMADA
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Patent number: 9431326Abstract: In a semiconductor device, semiconductor chips and lead frames are soldered at the same time on an insulating circuit board by one reflow soldering, and the positions of the externally led out lead frames undergo no change. In manufacturing the semiconductor device, after power semiconductor chips and control ICs are mounted on an insulating circuit board, and lead frames are disposed thereon, the semiconductor chips and lead frames are soldered at the same time on the insulating circuit board by one reflow soldering. Furthermore, after a primary bending work is carried out on the lead frames, and a terminal case is mounted over the insulating circuit board, a secondary bending work is carried out on the lead frames.Type: GrantFiled: March 30, 2012Date of Patent: August 30, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventors: Toshio Denta, Tadanori Yamada, Eiji Mochizuki
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Patent number: 9406576Abstract: A miniaturized semiconductor device includes a frame body having an opening region formed in a central portion, an insulating substrate which is provided in the opening region of the frame body and on which semiconductor chips are mounted, lead portions, each including an inclined portion that is at least partially exposed to the opening region formed in the frame body and extends so as to be inclined with respect to an end surface forming the opening region, and a bonding wire that is bonded between the lead portion and the semiconductor chip by ultrasonic bonding.Type: GrantFiled: March 12, 2015Date of Patent: August 2, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventors: Tadanori Yamada, Toshio Denta, Tomonori Seki
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Publication number: 20160211202Abstract: A miniaturized semiconductor device includes a frame body having an opening region formed in a central portion, an insulating substrate which is provided in the opening region of the frame body and on which semiconductor chips are mounted, lead portions, each including an inclined portion that is at least partially exposed to the opening region formed in the frame body and extends so as to be inclined with respect to an end surface forming the opening region, and a bonding wire that is bonded between the lead portion and the semiconductor chip by ultrasonic bonding.Type: ApplicationFiled: March 31, 2016Publication date: July 21, 2016Inventors: Tadanori YAMADA, Toshio DENTA, Tomonori SEKI
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Patent number: 9379096Abstract: A semiconductor device includes a plurality of semiconductor elements; first semiconductor chips including first semiconductor elements, the first semiconductor elements being defined as semiconductor elements in the plurality of semiconductor elements and having a current flowing greater than that of the other semiconductor elements; second semiconductor chips having second semiconductor elements, the second semiconductor elements being defined as semiconductor elements in the plurality of semiconductor elements for controlling the first semiconductor elements; an insulating substrate having a first wiring pattern bonded with the first semiconductor chips; and an insulating member having a second wiring pattern mounted with the second semiconductor chips.Type: GrantFiled: September 11, 2014Date of Patent: June 28, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventors: Toshio Denta, Tomonori Seki, Tadanori Yamada, Tadahiko Sato
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Publication number: 20150187669Abstract: A miniaturized semiconductor device includes a frame body having an opening region formed in a central portion, an insulating substrate which is provided in the opening region of the frame body and on which semiconductor chips are mounted, lead portions, each including an inclined portion that is at least partially exposed to the opening region formed in the frame body and extends so as to be inclined with respect to an end surface forming the opening region, and a bonding wire that is bonded between the lead portion and the semiconductor chip by ultrasonic bonding.Type: ApplicationFiled: March 12, 2015Publication date: July 2, 2015Inventors: Tadanori YAMADA, Toshio DENTA, Tomonori SEKI
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Patent number: 9064818Abstract: A semiconductor device includes an insulating circuit substrate mounted with at least one semiconductor element; a resin case having a bottom surface portion attached with the insulating circuit substrate and a side surface portion enclosing a periphery of the bottom surface portion; a lead molded integrally with the resin case and provided on a periphery of the insulating circuit substrate to be positioned on a surface of the bottom surface portion inside the resin case, the lead partially extending from inside the resin case to outside the resin case; and a sealing resin filled inside the resin case. A depressed portion is formed on two sides of the lead along a peripheral edge of the bottom surface portion inside the resin case.Type: GrantFiled: February 14, 2014Date of Patent: June 23, 2015Assignee: FUJI ELECTRIC CO., LTD.Inventors: Toshio Denta, Tomonori Seki, Tadanori Yamada, Tadahiko Sato
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Publication number: 20140374889Abstract: A semiconductor device includes a plurality of semiconductor elements; first semiconductor chips including first semiconductor elements, the first semiconductor elements being defined as semiconductor elements in the plurality of semiconductor elements and having a current flowing greater than that of the other semiconductor elements; second semiconductor chips having second semiconductor elements, the second semiconductor elements being defined as semiconductor elements in the plurality of semiconductor elements for controlling the first semiconductor elements; an insulating substrate having a first wiring pattern bonded with the first semiconductor chips; and an insulating member having a second wiring pattern mounted with the second semiconductor chips.Type: ApplicationFiled: September 11, 2014Publication date: December 25, 2014Inventors: Toshio DENTA, Tomonori SEKI, Tadanori YAMADA, Tadahiko SATO
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Publication number: 20140231975Abstract: A semiconductor device includes an insulating circuit substrate mounted with at least one semiconductor element; a resin case having a bottom surface portion attached with the insulating circuit substrate and a side surface portion enclosing a periphery of the bottom surface portion; a lead molded integrally with the resin case and provided on a periphery of the insulating circuit substrate to be positioned on a surface of the bottom surface portion inside the resin case, the lead partially extending from inside the resin case to outside the resin case; and a sealing resin filled inside the resin case. A depressed portion is formed on two sides of the lead along a peripheral edge of the bottom surface portion inside the resin case.Type: ApplicationFiled: February 14, 2014Publication date: August 21, 2014Applicant: FUJI ELECTRIC CO., LTD.Inventors: Toshio DENTA, Tomonori SEKI, Tadanori YAMADA, Tadahiko SATO
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Patent number: 8804316Abstract: A package includes a base member and a lid member joined to the base member while forming, between the lid and base members, an internal space which stores an electronic component. A joined section of the base and lid members includes a first welded section formed by joining the base and lid members along an x axis direction using seam welding and a second welded section formed by joining the base and lid members along a y axis direction using the seam welding. In plan view, the first and second welded sections do not overlap each other. An area where an area formed by extending the first welded section in the x axis direction and an area formed by extending the second welded section in the y axis direction overlap each other is located on the outer side with respect to the contour of the lid member.Type: GrantFiled: July 2, 2012Date of Patent: August 12, 2014Assignee: Seiko Epson CorporationInventors: Manabu Shiraki, Tadanori Yamada, Kazumi Hara, Kazuhiko Shimodaira
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Publication number: 20130334672Abstract: In a semiconductor device, semiconductor chips and lead frames are soldered at the same time on an insulating circuit board by one reflow soldering, and the positions of the externally led out lead frames undergo no change. In manufacturing the semiconductor device, after power semiconductor chips and control ICs are mounted on an insulating circuit board, and lead frames are disposed thereon, the semiconductor chips and lead frames are soldered at the same time on the insulating circuit board by one reflow soldering. Furthermore, after a primary bending work is carried out on the lead frames, and a terminal case is mounted over the insulating circuit board, a secondary bending work is carried out on the lead frames.Type: ApplicationFiled: March 30, 2012Publication date: December 19, 2013Applicant: FUJI ELECTRIC CO., LTDInventors: Toshio Denta, Tadanori Yamada, Eiji Mochizuki
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Publication number: 20130010412Abstract: A package includes a base member and a lid member joined to the base member while forming, between the lid and base members, an internal space which stores an electronic component. A joined section of the base and lid members includes a first welded section formed by joining the base and lid members along an x axis direction using seam welding and a second welded section formed by joining the base and lid members along a y axis direction using the seam welding. In plan view, the first and second welded sections do not overlap each other. An area where an area formed by extending the first welded section in the x axis direction and an area formed by extending the second welded section in the y axis direction overlap each other is located on the outer side with respect to the contour of the lid member.Type: ApplicationFiled: July 2, 2012Publication date: January 10, 2013Applicant: SEIKO EPSON CORPORATIONInventors: Manabu SHIRAKI, Tadanori YAMADA, Kazumi HARA, Kazuhiko SHIMODAIRA
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Patent number: 7859083Abstract: A semiconductor device is provided with Zener diodes which are formed by using a polysilicon gate layer(s) so as to be connected to each other in parallel. Parallel-connected rectangular Zener diodes are formed outside an active region or parallel-connected striped Zener diodes are formed inside the active region. The Zener diodes increase the ESD capability of the semiconductor device.Type: GrantFiled: August 8, 2008Date of Patent: December 28, 2010Assignee: Fuji Electric Systems Co., Ltd.Inventors: Takeyoshi Nishimura, Takashi Kobayashi, Yasushi Niimura, Tadanori Yamada
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Publication number: 20090039432Abstract: A semiconductor device is provided with Zener diodes which are formed by using a polysilicon gate layer(s) so as to be connected to each other in parallel. Parallel-connected rectangular Zener diodes are formed outside an active region or parallel-connected striped Zener diodes are formed inside the active region. The Zener diodes increase the ESD capability of the semiconductor device.Type: ApplicationFiled: August 8, 2008Publication date: February 12, 2009Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventors: Takeyoshi NISHIMURA, Takashi KOBAYASHI, Yasushi NIIMURA, Tadanori YAMADA
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Patent number: D674760Type: GrantFiled: August 22, 2011Date of Patent: January 22, 2013Assignee: Fuji Electric Co., Ltd.Inventors: Eiji Mochizuki, Toshio Denta, Tadanori Yamada