Abstract: In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

Abstract: In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

Abstract: In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

Abstract: In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

Abstract: A method for compensating for semiconductor device resistance is disclosed that includes the step of realizing a resistance equal to a desired resistance by one of combinations of multiple semiconductor devices. This step includes the step of sequentially selecting two or more of the semiconductor devices to be combined, and thereby sequentially changing a resistance realized by the selected two or more of the semiconductor devices to be combined.

Abstract: A method for compensating for semiconductor device resistance is disclosed that includes the step of realizing a resistance equal to a desired resistance by one of combinations of multiple semiconductor devices. This step includes the step of sequentially selecting two or more of the semiconductor devices to be combined, and thereby sequentially changing a resistance realized by the selected two or more of the semiconductor devices to be combined.

Abstract: In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

Abstract: A semiconductor memory that reduces power consumed by a CAM. A storage circuit has stored a plurality of patterns of information indicative of whether to activate each memory word block. If specification information for specifying a predetermined pattern from among the plurality of patterns of information which has been stored in the storage circuit is input, an activation circuit activates each content addressable memory word block according to a specified pattern. If data to be retrieved is input, a specification circuit specifies a content addressable memory word which has stored data corresponding to the data to be retrieved from among a group of content addressable memory words activated by the activation circuit. As a result, activation will be performed by the content addressable memory word block. Therefore, by activating only necessary content addressable memory words, consumption of power can be reduced.

Abstract: In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

Abstract: A semiconductor device including a parallel to serial conversion circuit that receives first through nth data (where n is an integer greater than or equal to 2), together with (n+1)th data, in parallel to each other, and that outputs the first through nth data in series in this order via first through nth paths in a first operating mode, while it outputs the (n+1)th data via one of the second through nth paths in a second operation mode. An output control circuit is connected to the parallel to serial conversion circuit via the first through nth paths, the output control circuit successively outputting the first through nth data in the first operating mode, and outputting only the (n+1)th data supplied from the parallel to serial conversion circuit in the second operating mode.

Abstract: This associative memory circuit comprises a plurality of logic circuits connected to a common match line. Each of the logic circuits compares a content stored in each of a plurality of memory cells with externally supplied search data so as to output a comparison result thereof to the match line. The associative memory circuit also comprises a reference-potential producing circuit provided correspondingly for the match line so as to produce a reference potential used in relation with the match line, and a differential amplifier circuit performing a differential amplification to a potential of the match line and the reference potential so as to judge whether or not the content matches the search data.

Abstract: A semiconductor memory that reduces power consumed by a CAM. A storage circuit has stored a plurality of patterns of information indicative of whether to activate each memory word block. If specification information for specifying a predetermined pattern from among the plurality of patterns of information which has been stored in the storage circuit is input, an activation circuit activates each content addressable memory word block according to a specified pattern. If data to be retrieved is input, a specification circuit specifies a content addressable memory word which has stored data corresponding to the data to be retrieved from among a group of content addressable memory words activated by the activation circuit. As a result, activation will be performed by the content addressable memory word block. Therefore, by activating only necessary content addressable memory words, consumption of power can be reduced.

Abstract: This associative memory circuit comprises a plurality of logic circuits connected to a common match line. Each of the logic circuits compares a content stored in each of a plurality of memory cells with externally supplied search data so as to output a comparison result thereof to the match line. The associative memory circuit also comprises a reference-potential producing circuit provided correspondingly for the match line so as to produce a reference potential used in relation with the match line, and a differential amplifier circuit performing a differential amplification to a potential of the match line and the reference potential so as to judge whether or not the content matches the search data.

Abstract: A semiconductor memory circuit includes a plurality of memory cell arrays arranged in rows and columns. A decoder circuit selects a predetermined number of memory cell arrays from among the plurality of the memory cell arrays. Sense amplifiers sense data read from selected memory cell arrays. The plurality of memory cell arrays are grouped into a first type of memory cell arrays each having a redundant memory cell and a second type of memory cell arrays each having no redundant memory cell.

Abstract: The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.

Abstract: A semiconductor memory circuit includes a plurality of memory cell arrays arranged in rows and columns. A decoder circuit selects a predetermined number of memory cell arrays from among the plurality of the memory cell arrays. Sense amplifiers sense data read from selected memory cell arrays. The plurality of memory cell arrays are grouped into a first type of memory cell arrays each having a redundant memory cell and a second type of memory cell arrays each having no redundant memory cell.

Abstract: The present invention is a memory circuit for writing prescribed numbers of bits of write data, determined according to the burst length, in response to write command, comprising: a first stage for inputting, and then holding, row addresses and column addresses simultaneously with the write command; a second stage having a memory core connected to the first stage via a pipeline switch, wherein the row addresses and column addresses are decoded, and word line and sense amps are activated; a third stage for inputting the write data serially and sending the write data to the memory core in parallel; and a serial data detection circuit for generating write-pipeline control signal for making the pipeline switch conduct, after the prescribed number of bits of write data has been inputted. According to the present invention, in an FCRAM exhibiting a pipeline structure, the memory core in the second stage can be activated after safely fetching the write data in the burst length.

Abstract: A semiconductor memory circuit includes a plurality of memory cell arrays arranged in rows and columns. A decoder circuit selects a predetermined number of memory cell arrays from among the plurality of the memory cell arrays. Sense amplifiers sense data read from selected memory cell arrays. The plurality of memory cell arrays are grouped into a first type of memory cell arrays each having a redundant memory cell and a second type of memory cell arrays each having no redundant memory cell.

Abstract: In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

Abstract: A semiconductor memory device outputs data in synchronization with an external clock signal. The semiconductor memory device comprises a first frequency divider dividing a frequency of the external clock signal supplied thereto so as to generate a first internal clock signal; a delay circuit delaying the external clock signal; a second frequency divider dividing a frequency of a signal supplied from the delay circuit so as to generate a second internal clock signal; and a data control unit outputting the data according to the first internal clock signal and the second internal clock signal.