Patents by Inventor Tadashi Iguchi

Tadashi Iguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12137559
    Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.
    Type: Grant
    Filed: March 14, 2023
    Date of Patent: November 5, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Takuya Inatsuka, Tadashi Iguchi, Murato Kawai, Hisashi Kato, Megumi Ishiduki
  • Publication number: 20240292626
    Abstract: A semiconductor memory device includes a first stacked body that includes first insulating films and first conductive films alternately stacked in a first direction; first columnar bodies each including a first semiconductor structure extending through the first stacked body, the plurality of first columnar bodies being configured as memory cells; and a plurality of second columnar bodies that each include at least one conductor extending through the first stacked body in the first direction, and are each coupled to a corresponding one of the first conductive films and a stacked film including second, third, and fourth insulating films, wherein the second to fourth insulating films are provided between the at least one conductor and the first stacked body.
    Type: Application
    Filed: February 23, 2024
    Publication date: August 29, 2024
    Applicant: Kioxia Corporation
    Inventors: Kazuki SHOJI, Tadashi IGUCHI
  • Patent number: 12075620
    Abstract: A semiconductor memory device includes a substrate, conductive layers arranged in a first direction and extend in a second direction, a semiconductor layer extending in the first direction and opposed to the conductive layers, and n contact electrode regions arranged in a third direction. The n is a power of 2. The contact electrode region includes contact electrodes arranged in the second direction. The conductive layers include a first conductive layer and a second conductive layer that is an n-th conductive layer counted from the first conductive layer. The contact electrodes include a first contact electrode connected to the first conductive layer, a second contact electrode connected to the second conductive layer, and a third contact electrode disposed between them. The first contact electrode, the second contact electrode, and the third contact electrode are arranged in the second direction or the third direction.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: August 27, 2024
    Assignee: Kioxia Corporation
    Inventors: Natsuki Fukuda, Tadashi Iguchi
  • Publication number: 20240121962
    Abstract: According to one embodiment, a semiconductor device includes a stacked film with first insulating films and electrode layers alternately stacked in a first direction. The device further includes a columnar portion extending in the first direction and provided in a first region of the stacked film. The columnar portion forms memory cells at its intersections with the electrode layers. The device further includes a support column portion provided in a second region and extending in the first direction. A conductive plug is provided on a first electrode layer among the electrode layers in the second region. A first side surface of the support column portion faces a second side surface of the plug and the second side surface is concave in a direction toward the first side surface.
    Type: Application
    Filed: September 5, 2023
    Publication date: April 11, 2024
    Inventors: Satoshi NAGASHIMA, Shota KASHIYAMA, Tadashi IGUCHI, Takuya NISHIKAWA
  • Publication number: 20240099001
    Abstract: According to one embodiment, a semiconductor memory device has a first film and a stacked body on the first film. The stacked body includes insulating films and conductive films stacked in a first direction. A first pillar extends through the stacked body and has a first semiconductor portion and a first insulator portion on an outer peripheral surface. A plurality of second pillars extend in the stacked body and reach the first film. The second pillars each comprise an insulator material and have a bottom surface with a protrusion protruding into the first film. A third pillar extends in the stacked body between adjacent second pillars. The third pillar comprises a conductor material that is electrically connected to one of the conductive films of the stacked body.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 21, 2024
    Inventor: Tadashi IGUCHI
  • Publication number: 20230326859
    Abstract: Contact plugs extend along a first axis. Each contact plug includes a second conductor and a first insulator. A first insulator is between the first conductors and the second conductor. A lower face of each contact plug is in contact with an upper face of a unique one of the first conductors. A first one and second one of the contact plugs are adjacent along a second axis that crosses the first axis. A third one of the contact plugs is between the first and second contact plugs on the second axis, and is at a different position from positions of the first and second contact plugs on a third axis orthogonal to the first and second axes.
    Type: Application
    Filed: September 8, 2022
    Publication date: October 12, 2023
    Applicant: Kioxia Corporation
    Inventors: Natsuki FUKUDA, Tadashi IGUCHI
  • Publication number: 20230225123
    Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.
    Type: Application
    Filed: March 14, 2023
    Publication date: July 13, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Takuya Inatsuka, Tadashi Iguchi, Murato Kawai, Hisashi Kato, Megumi Ishiduki
  • Patent number: 11637116
    Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: April 25, 2023
    Assignee: Kioxia Corporation
    Inventors: Takuya Inatsuka, Tadashi Iguchi, Murato Kawai, Hisashi Kato, Megumi Ishiduki
  • Publication number: 20230088929
    Abstract: A semiconductor memory device includes a substrate including a first region and a second region, a plurality of first conductive layers, a first semiconductor layer disposed in the first region, an electric charge accumulating layer, a contact electrode disposed in the second region and connected to one of the plurality of first conductive layers, and a plurality of first structures and a plurality of second structures disposed in the second region. The first structure includes a second semiconductor layer opposed to the plurality of first conductive layers and including a semiconductor material in common with the first semiconductor layer, and a first insulating layer disposed between the plurality of first conductive layers and the second semiconductor layer and including an insulating material in common with the electric charge accumulating layer. The second structure does not include the semiconductor material or the insulating material.
    Type: Application
    Filed: August 22, 2022
    Publication date: March 23, 2023
    Inventors: Natsuki FUKUDA, Tadashi IGUCHI
  • Publication number: 20230090305
    Abstract: A semiconductor storage device includes a substrate having a memory region and a hook-up region arranged in a first direction and a plurality of memory structures arranged in a second direction intersecting the first direction. The plurality of memory structures include a plurality of conductive layers arranged in a third direction intersecting a surface of the substrate and extending in the first direction over the memory region and the hook-up region and a plurality of contact electrodes provided in the hook-up region and extending in the third direction to have an outer peripheral surface surrounded by a part of the plurality of conductive layers, each contact electrode being connected to any of the plurality of conductive layers. The hook-up region includes a first area and a second area arranged in the first direction. The first region includes a first contact electrode and a second contact electrode, and the second region includes a third contact electrode.
    Type: Application
    Filed: March 3, 2022
    Publication date: March 23, 2023
    Applicant: Kioxia Corporation
    Inventors: Tadashi IGUCHI, Natsuki FUKUDA
  • Patent number: 11563026
    Abstract: A semiconductor storage device includes: a substrate having a front surface; a plurality of conductive layers arranged in a first direction, the first direction intersecting the front surface of the substrate; a plurality of memory cells connected to the plurality of conductive layers; a contact electrode extending in the first direction and connected to one of the plurality of conductive layers; and an insulating structure extending in the first direction, the insulating structure connected to an end portion of the contact electrode on one side of the contact electrode in the first direction, and penetrating the plurality of conductive layers.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: January 24, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Tadashi Iguchi
  • Publication number: 20220285389
    Abstract: A semiconductor memory device includes a substrate, conductive layers arranged in a first direction and extend in a second direction, a semiconductor layer extending in the first direction and opposed to the conductive layers, and n contact electrode regions arranged in a third direction. The n is a power of 2. The contact electrode region includes contact electrodes arranged in the second direction. The conductive layers include a first conductive layer and a second conductive layer that is an n-th conductive layer counted from the first conductive layer. The contact electrodes include a first contact electrode connected to the first conductive layer, a second contact electrode connected to the second conductive layer, and a third contact electrode disposed between them. The first contact electrode, the second contact electrode, and the third contact electrode are arranged in the second direction or the third direction.
    Type: Application
    Filed: August 9, 2021
    Publication date: September 8, 2022
    Applicant: Kioxia Corporation
    Inventors: Natsuki FUKUDA, Tadashi IGUCHI
  • Publication number: 20220020769
    Abstract: A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction.
    Type: Application
    Filed: October 1, 2021
    Publication date: January 20, 2022
    Applicant: Toshiba Memory Corporation
    Inventors: Tadashi Iguchi, Murato Kawai, Toru Matsuda, Hisashi Kato, Megumi Ishiduki
  • Publication number: 20210384214
    Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.
    Type: Application
    Filed: August 18, 2021
    Publication date: December 9, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Takuya INATSUKA, Tadashi IGUCHI, Murato KAWAI, Hisashi KATO, Megumi ISHIDUKI
  • Patent number: 11152391
    Abstract: A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: October 19, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tadashi Iguchi, Murato Kawai, Toru Matsuda, Hisashi Kato, Megumi Ishiduki
  • Patent number: 11127750
    Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: September 21, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Takuya Inatsuka, Tadashi Iguchi, Murato Kawai, Hisashi Kato, Megumi Ishiduki
  • Publication number: 20210280600
    Abstract: A semiconductor storage device includes: a substrate having a front surface; a plurality of conductive layers arranged in a first direction, the first direction intersecting the front surface of the substrate; a plurality of memory cells connected to the plurality of conductive layers; a contact electrode extending in the first direction and connected to one of the plurality of conductive layers; and an insulating structure extending in the first direction, the insulating structure connected to an end portion of the contact electrode on one side of the contact electrode in the first direction, and penetrating the plurality of conductive layers.
    Type: Application
    Filed: September 2, 2020
    Publication date: September 9, 2021
    Applicant: Kioxia Corporation
    Inventor: Tadashi IGUCHI
  • Publication number: 20200373327
    Abstract: A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction.
    Type: Application
    Filed: August 14, 2020
    Publication date: November 26, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Tadashi IGUCHI, Murato Kawai, Toru Matsuda, Hisashi Kato, Megumi Ishiduki
  • Publication number: 20200135750
    Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.
    Type: Application
    Filed: December 31, 2019
    Publication date: April 30, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Takuya INATSUKA, Tadashi IGUCHI, Murato KAWAI, Hisashi KATO, Megumi ISHIDUKI
  • Patent number: 10610784
    Abstract: A non-transitory computer-readable information storage medium storing a program that causes a computer to implement a game in which a first area of a virtual space that includes a maze-shaped path delimited by given virtual walls is allocated to a first player character that moves under the control of a first player, a second area of the virtual space is allocated to a second player character that moves under the control of a second player, and the first player character and the second player character compete for game progress in the respective areas allocated thereto.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: April 7, 2020
    Assignee: BANDAI NAMCO ENTERTAINMENT INC.
    Inventors: Toru Takahashi, Tadashi Iguchi